A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms

抄録

In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130nm 1P8M CMOS technology with a total area of 6.3mm² and maximum operating frequency of 250MHz. The chip dissipates 592mW when operates at 250MHz frequency and 1.2V supply.