Edge and Routability Aware Mapper for a Spatial CGRA

抄録

The coarse-grained reconfigurable architecture (CGRA) has been attracting significant attention as an energy-efficient accelerator. Recently, many applications require significant computational power, and CGRAs are expected to meet this demand. In such fields, CGRAs are utilized to execute computationally intensive programs in the innermost loop body, often called a “kernel”. They generally consist of a two-dimensional array of processing elements (PEs) interconnected in a configurable manner, and the data transfer between PEs is configured accordingly. Running a kernel on a CGRA requires a mapping process that generates CGRA configurations to match the kernel program. This mapping is time-consuming and can hinder developer productivity. We therefore propose a fast mapping method that leverages the architecture's characteristics, namely, its routing capabilities, to reduce mapping time. We define a heuristic cost function for routing that guides the mapper toward better mapping results. We demonstrate that our mapper is fast enough for practical software development and can provide sufficiently robust mapping results.