Loop Unrolling and DFG Partitioning for CGRAs: A Case Study of The Lattice Boltzmann Method

抄録

Driven by the strong demand for enhanced performance in High-Performance Computing (HPC), Coarse-Grained Reconfigurable Architectures (CGRAs) are promising technologies that offer high performance even under power consumption constraints. Performance on CGRAs is significantly influenced by loop unrolling, a technique that increases computational parallelism by utilizing more processing elements in CGRAs. Determining the optimal loop unrolling factor is challenging in applications with multiple loops. This paper presents a case study demonstrating the determination of optimal loop unrolling factors for an application based on the Lattice Boltzmann Method (LBM). Because the application's process exceeds the capacity of a single CGRA, this paper proposes a method for partitioning the process to fit the CGRA's resources using integer linear programming (ILP). Finally, this paper provides a performance estimation of the CGRAs runtime and demonstrates the effectiveness of CGRAs for HPC.