Reports of the Technical Conference of the Institute of Image Electronics Engineers of Japan
Online ISSN : 2758-9218
Print ISSN : 0285-3957
Reports of the 208th Technical Conference of the Institute of Image Electronics Engineers of Japan
Session ID : 03-07-12
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Multiple-valued Logic Circuits design for Image Contour Extraction
*Koichiro TSUJIAkinori MURANAKAShigeru IMANISHI
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Abstract
Multi-Valued logic system is introduced into the important preprocess of image recognition, and extracts image contour with it difficult to extract in processing of 2 value system generally used. Moreover, we compare our Multi-Valued logic circuit we designed with usual 2 value logic circuits. the miniaturization of circuits by curtailment of wiring count and transistor count ,and examine.
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© 2004 by The Institute of Image Electronics Engineers of Japan
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