PowerSynth has been developed to significantly accelerate power module design through a multi-objective layout synthesis and optimization process. It uses a series of layout generation and optimization algorithms and various electrical and thermal models to automatically synthesize power module layouts and create a Pareto surface of solutions with optimum electrical and thermal performance. Recent advanced power modules are designed with various types of components integrated on multiple device layers to minimize the parasitics and increase power density. With more compact layouts and tighter design constraints, power module design becomes increasingly challenging because of reliability and signal integrity issues, such as partial discharge, electromagnetic interference (EMI), electro migration, and noise-induced false turn-on. This paper summarizes the latest PowerSynth layout engine and model improvements with an emphasis on the new reliability and signal integrity features. A generic and scalable constraint-aware layout engine is developed to process generic types of devices, traces, and connectors in power modules. Electrical models are improved from a 1D wire model to a 2D mesh model with enhanced feature sets to better capture the intrinsic layout structures and extract coupling between power and gate loops. EMI models are built on top of it to further reduce the noise analysis and qualification requirement posted on designers. Finally, a new post-layout optimization step is included in the flow as an improvement of design for manufacturability and reliability. The software development along with the hardware testing results demonstrates the latest advances in design automation for power electronics.
We model the behavior of uniaxial ferroelectrics and simulate planar negative-capacitance (NC) field-effect transistors (FETs) having a gate insulating film made of a uniaxial ferroelectric. The behavior of such NC FETs strongly depends on the direction of the ferroelectric polarization axis. When the direction is away from being parallel to the ferroelectric film to some extent, the ferroelectric polarization becomes larger than the paraelectric polarization and the ferroelectric film begins to act as a negative capacitor. The NC FETs can then be switched on and off more steeply than conventional metal-oxide-semiconductor FETs. This NC effect is maximized at that moment and becomes weaker as the direction approaches perpendicular to the ferroelectric film.
Transient thermal characterization of power modules plays an important role in designing power conversion systems for miniaturization. Transient thermal network model of power module packages is identified by deconvolution calculation for the time response of junction temperature in power semiconductor devices, which is obtained by static test method. This paper develops a signal processing algorithm using weighted discrete Fourier transformation and noise filtering in frequency domain for nonuniform time step data in the converted logarithmic time domain to apply deconvolution calculation. The developed algorithm suppresses the influence of noise superimposed on the measured signal and enables the accurate identification of transient thermal network model.
In this paper, for the first time, an accurate glass package power distribution network (PDN) model is proposed for the PDN impedance estimation based on a segmentation method. To verify the proposed modeling method, glass package test vehicles including the PDN are fabricated. Estimated impedance of the glass package PDN based on proposed model is validated by comparing measured and simulated glass package PDN in the frequency domain up to 20 GHz. Estimated impedance based on proposed modeling method showed good correlation with measurement and 3-Dimensional electromagnetic (3D-EM) simulation. Compared to 3D-EM simulation, the proposed method is fast but accurate. Due to low loss of the glass package substrate, sharp PDN impedance peaks at mode resonance frequencies are generated. Signal and power integrity degradation at these frequencies are analyzed. Using the proposed modeling method, locations and frequencies where signal TGVs are less affected by the PDN mode resonances can be efficiently estimated for early stage package PDN design and signal TGV floor plan.
This paper proposes an analysis and design method of the phase-controlled class-D Zero-Voltage Switching (ZVS) inverter. To derive the ZVS region diagram, a steady-state waveform of the phase-controlled class-D inverter is analytically derived. This analysis introduces an expression of an anti-parallel diode behavior and multiple-harmonic analysis. By developing a ZVS region diagram at the fixed phase shift and drawing power contour lines over the region diagram, a parameter region, in which sufficient power can be obtained with achieving the ZVS, are also determined. The analysis and design method of this paper were verified through circuit experiments and by collating the quantitative values obtained from the experiment and analysis.
This paper presents a semi-analytical expression of the generalized class-E rectifier. Effect of low output-filter inductance is included in the theoretical formula presented in this paper. The harmonic components are considered in the current flowing through the output-filter inductance. For obtaining the theoretical waveforms, the coefficients of each frequency component are obtained by numerical calculations. By using the semi-analytical expression, characteristics of the class-E rectifier can be comprehended in a theoretical manner. By varying the output-filter inductance, it is possible to improve the rectifier characteristics, such as larger power output capability and zero input reactance, compared with the traditional class-E rectifiers. This paper also presents two examples of designs and implementations of resonant converters with the class-E rectifier. The validity of the semi-analytical expression and design strategies were confirmed from the quantitative agreements with experimental and PSpice simulation results.
Passive intermodulation distortion (PIMD) is a phenomenon in which two or more transmission signal frequencies interfere with each other due to non-linearity in passive elements of a wireless communication system and undesired signals are generated. Such intermodulation distortion increases the noise level in the receive frequency band of the wireless communication system, thereby degrading the performance of the receiver. In this paper, a PIMD mitigation scheme based on a modified cubic Volterra filter is proposed to reduce a passive intermodulation distortion level to enhance the uplink signal receive performance. The performance of the proposed approach is evaluated by applying it to the data sampled at a repeater for the long term evolution (LTE) system. The proposed approach demonstrates a notable reduction of PIMD in the receive band. The conventional least mean square (LMS) approach is considered in this study for the purpose of comparison.
As the amount of data that people handle increases, the conventional Neumann-type computer architecture is reaching its limits. Therefore, research on hardware implementation of machine learning systems is being actively conducted. In this paper, we have implemented and evaluated neuromorphic hardware that realizes human brain neurons and synapses using oxide semiconductor of amorphous In-Ga-Zn-O (a-IGZO) and a cellular neural network. It was confirmed how variations of initial resistance and deterioration rate of the oxide semiconductor affect operation accuracy of the neuromorphic hardware. Furthermore, we clarified that an activation function suitable for the hardware implementation is a ReLU function.
This paper proposes an effective thermal compact modeling method for a thin film resistor that is dedicated for snubber circuits in power electronic modules. The objective compact model consists of thermal capacitors and thermal resistors. Some of the objective compact models express the effects of local air gaps as well as convective boundary conditions, which are natively non-linear phenomena. To identify their values, we use the surface temperature response of the thin film resistor to the input power. The experimental results show that the derived compact thermal model robustly causes the measured thermal durability to wide input power pulse width variations to reappear.
This paper presents a numerical design approach of the load-independent class-E inverter with MOSFET gate-to-drain and drain-to-source parasitic capacitances. The design curves of the load-independent class-E inverter are also given. A design example is shown along with its LTspice simulation and laboratory experiment. By applying the proposed design approach, there are no changes in the output-voltage waveforms and all the switch-voltage waveforms satisfy the zero-voltage-switching (ZVS) condition even the load-resistance value varies from the desired one without applying any tuning processes. Additionally, the results obtained from the LTspice simulation and laboratory experiment show quantitative agreement with the numerical predictions, which shows the effectiveness of the proposed design approach and design curves of the load-independent class-E inverter with MOSFET gate-to-drain and drain-to-source parasitic capacitances given in this paper.