Proceedings of JIEP Annual Meeting
The 19th JIEP Annual Meeting
Session ID : 17A-10
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Local Distribution of Residual Stress in Si chip Assembled in Flip Chip Structures and Its Effect on Electronic Performance of Semiconductor Devices
*Nobuki UetaHideo Miura
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Abstract
Local residual stress at a surface of a silicon chip assembled to a substrate using area-arrayed metallic bumps was measured using a stress sensing chip. Both the maximum and the minimum principal stresses that occur in an assembled chip increase monotonically with decrease of a thickness of the chip. In addition, a periodic stress distribution occurs at the chip thinner than 200 micron . The amplitude of the stress reached about 150 MPa, when the thickness of the chip was thinned to 50 micron. In this case, the predicted maximum shift of electronic function of a PMOS transistor reached about 30%. Therefore, it is very important to minimize the amplitude of the residual stress to improve the reliability of products.
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© 2005 by The Japan Institute of Electronics Packaging
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