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Space charge behaviour in aramid/epoxy insulation was observed by using the pulsed electroacoustic method. Internal charges due to impurities of specimens appeared and accumulated at the interface between prepreg sheets. The charge quantity depends on the atmosphere, especially the humidity.

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Recently miniaturization and performance enhancement of electronic equipment are remarkable. The gap between the conductors on a printed circuit board becomes much smaller, and the high insulation reliability is required for the printed circuit board. In the printed circuit board, it is also abounding in the opportunity of which various surge are applied, and it is abounding of printed circuit board of which the inverter surge is always applied by the development of recent power electronics. From such background, surge dielectric strength between printed circuit board conductive foil was examined. The experiment was carried out by FR-4 model printed circuit board.

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We variousuly examine the genelation factor of whisker by the engagement of the connector according to lead free plating use,and report on the result of exmining the whisker prevention methods.As a result,thin plating Sn of FFC found the generation of whisker after the reflow being suppressed in the combination of the connector and FFC.Moreover,the intention to improvement Sn plating is preferable in the future though the Au plating is recommennded nou in the combination with FPC.The simple examination method was examined along with the above-mentioned content.

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The debates have now developed to the extent that a movement to establish regulations for the removal of Pb has emerged, in view of environmental problems. Therefore, many studies are being undertaken to develop technologies for replacing Sn-Pb solder with a lead-free alternative. However, the problem is that voids are easily formed in lead-free solder joints during the reflow process, and the effects of void formation on the fatigue strength of solder joints have attracted attention. In this study, the relationship between formation of voids and fatigue fracture mode and fatigue strength of solder joints was examined using FEM (finite element method) analysis and mechanical shear fatigue test.

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Damage path simulation, which corresponds to the estimation of thermal fatigue crack propagation behavior, was verified for solder joints in QFP (Quad Flat Package). It was clear that the extension of the damage path showed good agreement with the behavior of crack propagation observed in the actual thermal cycle test (TCT).

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[in Japanese]

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The pursuit of high fidelity and low cost Liquid Crystal Display (LCD) has made the pitch of bumps of LCD driver ICs finer. So finer pitch flexible circuits, on which the driver ICs are mounted, are required. But conventional flexible circuits have inadequate dimensional stability and insulating resistance for 30 micron pitch leads or less. We have improved these properties and realized 20 micron pitch flexible circuits with high dimensional stability and insulating resistance. We are also studying on 10 micron pitch flexible circuits.

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[in Japanese]

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As for the PWB of a portable product,it tends to become high density wiring and thinly. The warp of the PWB and PKG causes to unjoint and the bridge of the solder joint in the reflow process. This time, authors design the simple evaluation substrate, and shadow moire technique measurement and the numerical simulation for the temperature profile of the reflow are executed. Temperature dependent material properties are measured,and They are used for the simulation.Then,Authors reports the correlation of the simulation result and the measured value.The warp forecast of the substrate by the simulation become possible.

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[in Japanese]

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An opto-electronic hybrid integration platform with a polymer optical waveguide has been developed to realize compact and low-cost optical transceivers in metropolitan area networks and access networks. Since the new platform consists of a thick polymer resin insulator, which has low optical loss, low dielectric constant and low dielectric loss tangent, and of an electrical circuit, optical devices and front-end LSIs are mounted on a single platform, and also the number of module components and assembly cost can be reduced. The optical waveguide properties at wavelength of 1.3/1.55 micron are suitable for optical modules and the electrical responses are faster than 10Gbit/s.

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We report on the development of silicon microlenses. The proposed silicon microlens is passivley aligned with various optical devices on the silicon v-groove platform, enabling the mass production of the low-cost and yet hight performance optical components for both access and metro optical networks. The details of the microlens development will be reported at the conference. We will also discuss experimental results of the optical subassembly in which both laser diode and a microlens are aligned, and four-channel parallel fiber coupler.

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[in Japanese]

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In the three-dimensionally assembled structures of electronic systems, the thickness of each LSI chip has been thinned to less than 100 micron. This thinning of LSI chips, however, increases the local thermal deformation of each chip because of decrease of bending elasticity of the chip. The magnitude of the local deformation was calculated using a three-dimensional finite element analysis, and it exceeds 200 nm easily. Thus, it is possible to find out the position where a bump does not exist by comparing the deformation pattern of a regular structure with that of an irregular or defect structure. To confirm that the estimated local deformation of an LSI chip thinner than 100 micron is detectable, we applied a scanning blue laser microscope to measure the local deformation.

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Reliability of BGA type packages jointed with Sn-Ag-Cu solder (lead free) are investigated under impact load. It found out that the strength to impact differed greatly by the kind of solder mask material of the interposer board of BGA.

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Local residual stress at a surface of a silicon chip assembled to a substrate using area-arrayed metallic bumps was measured using a stress sensing chip. Both the maximum and the minimum principal stresses that occur in an assembled chip increase monotonically with decrease of a thickness of the chip. In addition, a periodic stress distribution occurs at the chip thinner than 200 micron . The amplitude of the stress reached about 150 MPa, when the thickness of the chip was thinned to 50 micron. In this case, the predicted maximum shift of electronic function of a PMOS transistor reached about 30%. Therefore, it is very important to minimize the amplitude of the residual stress to improve the reliability of products.

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[in Japanese]

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The availability of X-ray CT system for voids in Sn-3.0Ag-0.5Cu solder joint was evaluated. X-ray CT system was a non-destructive analysis and had a capability of setting cross-section at will. Voids were mainly observed at printed circuit board side in Sn-3.0Ag-0.5Cu solder joint. Area of voids at 245degC was larger than area of voids at 235degC or 240degC, maximum value of re-flow temperature. Therefore, X-ray CT system was useful for evaluation of voids in Sn-3.0Ag-0.5Cu solder joint.

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We developed the three-dimensional X-rays CT system which was suitable for inspecting a PCB.This system employed open tube type x-ray source and FPD, it can take three-dimentional CT photography of high-precision and high speed.We verified this system using defect sample of CSP and Chip parts. The result showed that defects could be expressed clearly.

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[in Japanese]

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