Proceedings of JIEP Annual Meeting
The 21th JIEP Annual Meeting
Session ID : 16A-11
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Effect of Bump-layout Structures on the Local Residual Stress in Three-dimensionally Stacked LSI Chips Mounted using Area-arrayed Flip Chip Technology
*Nobuki Ueta, [in Japanese], Hideo Miura
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Keywords: Residual stress, Reliability, Three-dimensionally stacked structure, Flip chip assembly
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Abstract
[in Japanese]
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© 2007 by The Japan Institute of Electronics Packaging
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