Sense amplifier driving scheme with adaptive delay line for reducing peak current and driving time variations in deep-sub-micron DRAMs

Abstract

In this letter, a simple but effective sense-amplifier driving circuit using adaptive delay line is proposed to suppress a high current peak occurring in enabling sense amplifiers at a fast Process-V_DD-Temperature (PVT) condition. And, this circuit also can improve a slow enabling time of sense amplifiers at a slow PVT corner. This new circuit is verified in recent 0.18-µm DRAM technology, where the variations in the sense-amplifier enabling time and peak current are suppressed from 72% to 1% and 240% to 28%, respectively, compared with the previous sequential sense-amplifier driving circuit.