This paper focuses on Hall-effect sensor fault detection and compensation for brushless dc (BLDC) drives. A methodology based on the Hall position vector phase differences is investigated to detect Hall fault. In order to obtain high-resolution position estimation in fault operation, an improved interpolation position estimation algorithm is described. The method’s most innovative feature is the rapid fault diagnosis. After that, Hall signal noise is analyzed between sampling periods, and a correction machine to filter Hall noise and compensate the filter delay is proposed. Experimental results are shown to validate the effectiveness of the proposed method in the BLDC drive system.

A new type of DC-DC converter has been devised: the Hybrid Boost Inductor-Diode-Capacitor (HB-LDC) converter. A novel switching structure, a diode, a capacitor and a switch were added into an elementary additional circuit, to construct the HB-LDC converter. The proposed switching structure that carries out the step-up function is composed of three inductors and six diodes. The HB-LDC converter depends mainly on charging and discharging of the inductors and capacitors to realize the step-up function. The continuous-conduction mode (CCM) operation for the HB-LDC converter is analyzed. When the HB-LDC converter works in CCM, the voltage gain is only related to the duty cycle. Theoretical analysis shows that the HB-LDC converter is characterized by high voltage gain, low switching stress, and low inductance ripple. The theoretical analysis was verified by the construction of a working device.

In this letter, a new filtering method for digital phase-locked loops (DPLLs) is proposed. The proposed method is based on finite impulse response (FIR) filtering, which estimates the state variables of a system using recent finite measurements. FIR filtering requires the optimal selection of a design parameter, the memory size, which has been cumbersome. A method to compute the optimal memory size has been proposed; however, it is ineffective when the noise information is uncertain. Thus, in this letter, a memory parameterized FIR filter (MPFF) is proposed to solve this problem, and the DPLL simulation results are presented for performance demonstration.

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique is proposed. With the variation of input signals, the parasitic capacitance variation of sampling switch is reduced and the total parasitic capacitance is also depressed. Moreover, with substrate boost technique, the on-impedance of sampling switch would decrease. To demonstrate the proposed technique, a design of 12-bit 100-MS/s SAR ADC is fabricated in 40-nm CMOS technology, consuming 2 mW from 1 V power supply with a SNDR >65 dB and SFDR >83 dB. The proposed ADC core occupies an active area of 0.02 mm², and the corresponding FoM is 13.8 fJ/conversion-step with Nyquist frequency.

In order to improve the higher rate of OLED-on-Silicon Micro-display, this paper proposes a high-efficient operator strategy, which is based on the cancel of waiting time. The theory structure of high-efficient operator is proposed through the relationship between sub-field sequences and bit sequence for different gray levels. This operator is tested using the IP core and self-built HD OLED micro-display system. The experiment shows that the high-efficient operator can obtain excellent scan utilization under idle condition, compared with the traditional scan methods.

This paper investigates the design space of a broadband continuous Class-F power amplifier (PA) at the device package plane. By parameterizing the empirical parameter by frequency, the extrinsic fundamental and second harmonic impedances can be engineered to rotate clockwise on the Smith chart which can be realized by the realistic matching network. The proposed design methodology is verified with the implementation of 10 W PA which operates across 1.7–3 GHz. The experimental results show that this PA can achieve drain efficiency of 54.7%–74.8% in the whole interesting band.

In this letter, NAND-based approximate half adder (NHAx) and full adder (NFAx) cells are proposed for low power approximate adders. NHAx and NFAx architectures are built using NAND logic gate which has a minimal normalized gate delay among all the CMOS based integrated circuit digital logic family; therefore, an improvement of 29% in the critical path delay is achieved. For the performance evaluation, 8-bit ripple carry adder (RCA) is then built using proposed cells. RCA-NFAx shows a good power-efficiency trade-off when both power delay product and error metric NMED are considered with reference to the previous approximate 1-bit FA based RCA designs.

This paper presents a compact, low-phase-noise and low-power D-band VCO with the tuning range from 140.1 to 143.5 GHz. To improve the area and power efficiency, we avoid using signal amplification and matching circuits in the VCO, where a 70 GHz LC oscillator is directly coupled to a frequency doubler. The layout of the transistors is optimized so that the signal loss and reflection are minimized. The proposed VCO fabricated in a 65 nm CMOS technology occupies the core area of 0.05 mm². It achieves the output power of −8 dBm and the phase noise of −108.2 dBc/Hz at 10 MHz offset with the power consumption of 24 mW from 1 V supply, which leads to the figure-of-merit (FoM) of −177.4 dBc/Hz.

Hybrid filter bank (HFB) is a promising technology that both improve the resolution and speed of digital-to-analog conversion. In this letter, we present a wideband waveform generation method using HFB architecture. Mixers are adopted to break through the limitation caused by zero-order-hold (ZOH) of DACs. However, the imperfect match of analysis filters and synthesis filters significantly degrade the system performance. To solve this problem, we analyze the influence of filter mismatch. An analysis filter design based on weighted least squares (WLS) and an optimization design for synthesis filter is presented. The optimization method invokes the WLS method at each iteration. Performance evaluation shows that these two methods work together and perform a better reconstruction system than the WLS method which just focus on analysis filter bank.

In this paper, an interface circuit based on parallel-synchronous switch harvesting on inductor (SSHI) is proposed for piezoelectric and thermoelectric energy harvesting. The proposed interface circuit could harvest power from piezoelectric transducers (PZT) and thermoelectric generators (TEG) simultaneously with a single-shared inductor. In addition, the harvester enables cold start without external battery. Simulation results indicate that the proposed circuit has higher power extraction capability by increasing damping force of the PZT, and the overall output power is 15.8% higher than conventional SSHI harvester when the load resistor is 10 KΩ.

In this letter, odd-mode and even-mode spoof surface plasmon polaritons (SSPPs) supported by complementary plasmonic metamaterial with underlayer ground are investigated. The dispersion characteristics and electric field distributions of the odd-mode and even-mode SSPPs are studied. Different high-efficiency conversion structures are proposed to realize the excitation of odd-mode and even-mode SSPPs transmissions. The odd-mode and even-mode SSPPs transmission lines are simulated and measured. The measured insertion losses of odd-mode transmission line are within 2.58 ± 1.23 dB from 3.0 to 10.0 GHz. The measured insertion losses of even-mode transmission line are within 1.66 ± 1.18 dB from 2.0 to 12.0 GHz. The simulation and measurement results validate the high-efficiency excitation and excellent propagation performance of odd-mode and even-mode SSPPs on the complementary plasmonic metamaterial with underlayer ground in the microwave frequencies.