Conformal shielding, as an efficient method for solving the electromagnetic interference (EMI) problem, is becoming increasingly important. In this Letter, the Taguchi method in quality engineering was introduced into the design optimization of conformal shielding. As a pilot test, the authors studied the order of the effects of shielding layer material, shielding layer thickness, and distance between ground vias (D-via) on shielding effectiveness (SE). The comparison between simulated results and predicted results proves that the optimization method is accurate and effective. The thin-film conductivity of copper was measured, and the model was revised using the measurement results. For validation, built a near-field scanning platform, and measured shielding effectiveness and simulated shielding effectiveness show a good agreement from 0.1 to 7.5 GHz.

Power delivery network (PDN) impedance reduction is strongly required for recent high-performance graphical-processing-unit, and mobile electronics that requires massive data transfer among logic and memory dice. To improve PDN characteristics, low equivalent series inductance and resistance (ESL and ESR) are required for capacitor, as well as powerline routing including placement of the capacitor. In this paper, we focus on Si-interposer as a method to enable ultra-high bit rate as well as fan-out wafer level packaging. A Si-interposer with transmission lines is manufactured, and CMOS test vehicle and low ESL Si-capacitors are mounted on the Si-interposer to evaluate chip-to-chip communication performance on multi-chip-module (MCM), through evaluating powerline noise. Experimental results of in-place waveform with physically different capacitor types and placements on Si-interposer, by on-chip waveform monitoring (OCM) technology. PDN analysis clarified the efficacy of low profile Si-capacitors and placement strategy to minimize series parasitic components, captured waveform shows stabilized drain power voltage (VDD) waveshape through 12-channels low-voltage differential signaling (LVDS) transceivers operation.

In this paper, aiming at the known or unknown uncertainties in permanent magnet linear synchronous motor (PMLSM) servo system, an intelligent backstepping terminal sliding mode control (IBTSMC) method is proposed for accurate position tracking of the servo system. The designed controller makes use of the advantage of backstepping terminal sliding mode control theory to ensure fast convergence and robustness. Finally, the stability analysis is carried out by using Lyapunov stability theory, and the effectiveness of the designed control scheme is proved by experiments.

The Itoh-Tsujii inversion algorithm forms a major contribution in finding the inverse in cryptographic applications such as Elliptic Curve Cryptography. In this paper, a new Hex Itoh-Tsujii inversion algorithm is proposed to compute the multiplicative inverse efficiently on Field-Programmable Gate-arrays (FPGA) platforms for binary fields generated by NIST recommended irreducible trinomials. The Hex Itoh Tsujii inversion Algorithm based proposed architecture is constructed with hex circuits and quad addition chain. This combination improves the resource utilization. The experimental results shows that the proposed work has better Area-Time Performance compared with the existing implementation.

An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking technique based on neural network is presented in this work. In order to minimize loop bandwidth variations, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a controllable phase error scaling module. Biasing voltages of varactor and the control word of the phase error scaling module are trained by the neural network and updated. The proposed technique can maintain a constant loop bandwidth over operating frequencies from 1.6-2GHz with variation varying from -2.66～3%.

The traditional direct LDPC encoder in CCSDS standard for space application needs to store the first row in each submatrix of the generator matrix, making the circuit implementation complex. To solve this problem, a low-complexity encoder for LDPC codes is implemented in this letter. The encoder stores the vector in random-access memory (RAM). To implement the multiplication of sparse matrix and vector with limited hardware resources, the encoder takes the row indexes of nonzero entries in each column of sparse matrix as the write address of the RAM. Moreover, the shift-register-adder-accumulator is exploited to implement the multiplication of the dense core matrix and the vector, greatly reducing the storage and computation complexity. The LDPC encoder with the code rate of 1/2 in the CCSDS standard is implemented on Xilinx XC6VLX240T FPGA chip, and the implementation results indicate that the proposed encoder consumes 50% less hardware resources than the traditional direct encoder.

Solid-state drives (SSDs) for mobile and embedded systems may not provide very high performance by today’s standards; however, they are small, low cost and consume little power. SSD controllers are thus designed as DRAM-less chips. SRAM cells created by the IC foundry as a standard module are embedded in the SSD controller as data buffer and can be single-port or two-port. In an SSD controller, more than two IPs simultaneously access the same SRAM, such as the CPU, data interface, and multiflash memory channel. It is thus complicated to exchange data between multiple ports. A new architecture of the multi-port data buffer (M-Buffer) is proposed in this study to solve this problem. M-Buffer is composed of wide SRAM, a smart arbitrator and several interface port logics. The M-Buffer can be designed as a reusable architecture and is small, low cost and consumes little power.