In order to explore the improvement of IGBT devices with high performance and low loss by unilateral local lifetime control, this paper uses Sentaurus TCAD simulation to compare the effects of overall and unilateral local lifetime control on the performance of insulated gate bipolar transistor. The results show that the unilateral local lifetime control achieves a good compromise in the characteristics of IGBT, especially when the lifetime control area is close to the N-buffer layer, the overall performance of IGBT is the most superior. Further research on unilateral localized lifetime control shows that by reducing the minority carrier lifetime and increasing the width of the lifetime control region at the same time, the turn-off loss of the device can be reduced, but the on-state voltage drop can also be increased. When the width of the one-sided local lifetime control region is 20μm and the minority carrier lifetime is 15ns, the relationship between the two can be well balanced, which provides a reference for the design and optimization of IGBT.

In wireless power transfer (WPT) systems, it is well known that the series-parallel (SP)-compensated topology is preferable for large load systems, like biomedical implants and consumer electronics, etc. However, it is a major challenge for practical SP-compensated WPT applications to obtain efficient and stable power transfer characteristics under the variations of coupling coefficient and resonant frequency. Therefore, based on fractional-order (FO) circuit theory, this paper proposes an SP-compensated FOWPT system with coupling independence and detuning insensitivity. Experimental results show that stable output power is maintained with a constant transfer efficiency in a wide load range, and when the resonant frequency of the receiver is detuned ±5%, the fluctuations of output power and transfer efficiency are less than 1%. The experiment validates the effectiveness of the proposed system.

In this letter, a new extraction method of GaN switch-HEMT small-signal model with capacitance scanning algorithm is proposed. In the algorithm, the proportional relationship among intrinsic C_gs, C_gd and parasitic C_g is scanned based on a simplified small-signal model without any approximations for capacitance. Comparing with the measured S parameters, optimized model parameters with the minimum error, especially the parasitic C_g, are achieved without assistance of extra methods such as EM analysis. Using this method, the accurate small-signal model for a 0.25μm gate-length GaN switch-HEMT up to 26.5GHz is extracted. This convenient method can be used for both GaN and GaAs switch-HEMT.

This paper presents a transparent super-wideband (SWB) MIMO antenna based on a metal mesh structure. The metal patch and substrate of the antenna are hollowed out, resulting in a transparency of up to 77% and a radiation efficiency exceeding 82%. The bandwidth of this MIMO antenna ranges from 1.6 to 19.2 GHz, achieving a bandwidth ratio of 12: 1. An engineered parasitic decoupling structure ensures that the isolation between antenna elements is greater than 25 dB, and the envelope correlation coefficient (ECC), diversity gain (DG), channel capacity loss (CCL), and total active reflection coefficient (TARC) all reach good values.

This letter proposes a broadband high-efficiency quasi Class E internally matched power amplifier with a compact bandpass output matching structure. By setting all the harmonic impedances following the ideal Class E mode, a specific load-pull analysis is employed to achieve the optimum fundamental impedance region with both high power and high efficiency. In order to further improve the efficiency of the power amplifier, high-efficiency second harmonic impedance range is obtained by the similar load-pull analysis. A compact bandpass matching structure with only three inductors and two capacitors is utilized to realize a broadband output matching of the broadband Class E mode power amplifier. No additional choke inductor is needed for our design, which further reduces the size of the circuit. A compact broadband quasi Class E GaN power amplifier is designed and fabricated using an internal matching method. The drain efficiency of 71% to 76% is achieved at 1.3GHz to 2.0GHz, with an output power of 10W and a power gain of more than 11dB.

This letter introduces a fully integrated broadband dual-mode reconfigurable driver amplifier (DA). DA can operate in analog DA mode (ADA-mode) and digital DA mode (DDA-mode) to meet different requirements for linearity and efficiency in various scenarios. A broadband reconfigurable output network enables the DA to operate from 2–4.5 GHz providing impedance matching, power combining and harmonic rejection. The DA offers a maximum gain of 12 dB with a 5-bit digital-control gain step in 1.6 V supply. Measurement results demonstrate that the DA achieves an OP1dB of 8.5 dBm with a drain efficiency of 13.1% in ADA-mode. In DDA-mode, the DA achieves a maximum output power of 10 dBm with a drain efficiency of 30.8%. The gain error of proposed DA is less than 0.3 dB. The DA is fabricated in 40 nm CMOS process, and the active area is 0.16 mm².

In this paper, an improved coverage optimization method for video sensor networks(VSNs) based on Whale optimization algorithm (SGWOA) is proposed to solve the problem of uneven distribution of nodes in random deployment of video sensor networks, which will cause coverage holes or coverage redundancy in the coverage area of VSNs. Firstly, Sobol sequence is used to initialize the population, which improves the diversity of the population and makes the distribution of network nodes more uniform when randomly deployed. Secondly, the nonlinear convergence factor and adaptive inertia weight are introduced to prevent the algorithm from falling into local optimal prematurely. Finally, Levi's flight strategy is added to disturb the position update during whale optimization, which speeds up the convergence of the algorithm and avoids premature convergence.

To improve the performance of permanent magnet synchronous motor ( PMSM ), a single closed-loop active disturbance rejection control strategy of permanent magnet synchronous motor based on compensation function is proposed in this paper. Firstly, a single closed-loop linear active disturbance rejection controller is designed to reduce the difficulty of controller parameter tuning. Secondly, the control effect of the active disturbance rejection control method is optimized by combining the compensation function observer (CFO) with the linear active disturbance rejection control (LADRC), and the current limiting control link is designed to ensure that the motor works within the current constraint. Finally, the stability analysis is carried out, and the control strategy is simulated and the prototype experiment is carried out. The results show that compared with the traditional LADRC, the improved method has a simple control system structure, strong anti-interference ability to load and parameter changes, and the controller adjustment is simple and easy to implement in engineering.

In this work, a low-complexity encoder is designed and implemented for LDPC codes in the GPS-L1C standard. By using the structural properties of parity-check matrices, we propose a backward substitution encoding method based on look-up-tables for calculating parity-check bits, which avoids the storage of the inverse matrices recommended by the GPS-L1C standard. As a result, the storage requirement and the encoding delay are reduced. The implementation results in 65 nm process indicate that the designed encoder circuit area is 5869.44 µm², the number of equivalent gates is 2006, the storage is 600 bits, and the delay is 60 cycles.

This paper presents a low-dropout linear regulator (LDO) with ultra-low quiescent current in high-voltage environments. A high-voltage pre-regulation module is employed to provide stable low-voltage output, reducing the use of high-voltage transistors. The integration of error amplifiers and reference circuits effectively reduces quiescent current while reducing chip area. Load detection function is used to reduce the quiescent current of the over temperature protection circuit under no-load conditions. Stability within the full load range is achieved through zero-pole tracking compensation and pseudo-ESR compensation techniques. LDO is fabricated using 0.35 μm BCD high-voltage technology and can stably output 5 V when the input voltage is in the range of 5.5-24 V. The quiescent current at 24 V input is 960 nA, and it can drive a maximum load of 150 mA. The overshoot voltage is less than 61 mV during load variations within 100 mA.

A laboratory test platform was established to explore the impact of humidity on potential-induced degradation (PID) under ash-covered photovoltaic modules. The mechanism behind changes in leakage current and output power was thoroughly investigated. The results indicate that the combination of dust accumulation on the module surface and humidity significantly elevates the leakage current. Specifically, the leakage current experiences an exponential increase when humidity exceeds 45% (CRH).By utilizing Peck's equation, the correlation coefficient λ between the power degradation of dust-covered and clean modules was derived. This coefficient can accurately forecast the power loss of dust-covered modules, offering valuable insights for the maintenance of PV power stations.

A direct torque control (DTC) strategy tailored for switched reluctance motor (SRM) with ring winding structure is proposed. In the proposed topology, stator voltage vectors are reconstructed, and explain the working modes of the SRM. Estimating the reference circulating current by a neural network, that flux magnitude and torque as inputs. With which, ensuring consistent direction of the three-phase winding currents. Circulating current control system and DTC control system of SRM with ring winding structure. Compared the performance of the SRM under various operating conditions in Simulink, validating the effectiveness of the control system.

This paper proposes a high step-up DC-DC converter with a quadratic cascaded coupled inductor. The primary and secondary sides of the coupled inductor are connected in series, and the secondary side of the coupled inductor is combined with the voltage multiplier cell. The main advantages of the converter include high voltage gain, low voltage stress on power switches, continuity of input current, and the common ground between the source and load. The performance of the proposed converter is experimented with using a 220W prototype that converts 25V from the input side to 426V on the output side. The peak efficiency is up to 94.77 %.

A 12-bit successive approximation register-based analog-to-digital converter (SAR ADC) with non-binary search technology is introduced. By embedding redundant weights in the branch capacitors of traditional binary DAC arrays, non-binary search can be achieved without adding additional control logic. Enables fast conversion with low overhead and tolerates the problem of incomplete stability of the reference voltage. Divide the MSB capacitor equivalently and use a hybrid capacitor switch to reduce the power consumption of the comparator and the changes in input common mode voltage (VCM). The total capacitance is reduced through the use of dual reference, avoiding the mismatch caused by the use of small unit capacitance. The ADC achieves an SFDR of 75.61dB and 10.22-bit ENOB with Nyquist input consuming 1.83mW at 1.1V supply, resulting in a figure of merit of 30.69fJ/conversion step.

This study develops new technology for detecting metal foreign objects to enhance the safety of wireless charging systems. The intrusion of metal objects during charging may result in reduced performance, increased energy consumption, and excessive heat generation, which may potentially damage the charging system. In this paper, we develop an innovative sensorless method of detecting foreign objects. We build an efficiency model by conducting experiments with metal objects of various sizes placed between charging coils. This approach identifies metal objects on the basis of efficiency changes, eliminating the need for sensors, thus effectively reducing costs. Finally, the effectiveness and reliability of this model are validated using the experimental platform.

The laser power transfer (LPT) system is one of the most promising systems in the long-rang wireless power transfer field. An interesting extension of LPT technology is the combination with optical communication. However, traditional optical communication technology for LPT system suffers from crosstalk issue, which leads to instability of power transmission and inaccuracy of data decoding in practical application. In this paper, a data modulation method is proposed to guide the modulation process of laser input current. Thus, the data can be directly incorporated into the optical power delivery path without inducing power fluctuation at receiver. Furthermore, based on the proposed data modulation method, a laser power supply consisting of a constant-current converter and a bidirectional converter is employed. It is possible that the desired modulated laser input current may be affected by the laser input voltage due to the bandwidth limitation of the laser power supply. Thus, a feed-forward scheme is also introduced to ensure the laser power supply can output desired modulated current. Finally, the experimental results are shown to validate the theoretical analysis.

This paper proposes a new α algorithm based on Lagrange linear interpolating power prediction. This algorithm ameliorates the conventional power prediction perturbation and observation method, thus enhances system accuracy and reduces errors. Meanwhile, it also has relatively faster transient tracking speed and smaller oscillation than the traditional method. By iteratively tracking the intermediate variable α, the algorithm operating point is close to the factual maximum power point, which can shorten the tracking time. Furthermore, when the external environment changes, Lagrange linear interpolating power prediction method can avoid misjudgments effectively. The algorithm has been verified using Matlab/Simulink software and through experimentation.

Weak resistive defects in standard cells exhibit subtle electrical behaviour that may lead to test escapes, thereby compromising the reliability of integrated circuits. Fault analysis data has shown that the presence of weak defects in specific cells can cause variations in output timing when multiple transitions occur on the inputs, as opposed to a single transition. However, existing delay test generation tools do not account for the effect of multiple input switching (MIS). In this paper, the effects of MIS on defect detection and timing analysis are analyzed and a multi-transition delay test method is proposed to further expose and detect cell internal defects. In addition to sensitizing the selected paths, the new test pattern attempts to maximize the off-path input transitions, thus increasing the propagation delay of the selected paths or the proportion of incremental delay introduced by the defects. The simulation results on ISCAS benchmark circuits show that the proposed method achieves a maximum of 8.73% and an average of 5.99% defect coverage gain compared to the existing delay tests that based on single input switching schemes.

An accurate and efficient electromagnetic (EM) modeling approach based on Neuro-space mapping (Neuro-SM) is proposed for substrate integrated suspension line (SISL) devices. A new coarse model containing 1 layer of dielectric plates, 2 layers of metal plates and 2 air cavities are developed to accelerate EM model simulation speed. To improve EM model accuracy, a parameter mapping network and a frequency mapping network are added into the structure. The EM responses of the SISL devices are taken as the fine model, while the proposed coarse model and two mapping networks are considered as the advanced Neuro-SM model. A three-step training process is developed to reduce errors between the fine and Neuro-SM model. The reasonable Neuro-SM model structure and efficient training algorithm greatly simplify the SISL device modeling process and further shorten the SISL device design cycle. The experimental results of a low-pass filter with SISL structure show that the training and test errors of the proposed model are 1.1% and 1.3%, which proves that the established model could accurately represent the characteristic of the SISL device.

This paper proposes a directly coupled instrumentation amplifier (IA) for EEG signal acquisition. By integrating both chopping and auto-zeroing (AZ) techniques, an offset and 1/f noise control loop (OFC) structure is proposed. Furthermore, a Capacitive Impedance Boost Loop (CIBL) configuration is presented to augment the input impedance within the EEG frequency band. Using the Common-Mode Biasing Circuit, the common mode rejection ratio (CMRR) of the circuit is improved. Fabricated in a 180-nm CMOS process, the prototype IA has the input-referred noise of 0.12 µV_rms from 0.01 Hz to 100 Hz. The proposed IA achieves high-input impedances of 4.14 GΩ at 20 Hz , and CMRR of 133.1 dB at 70 Hz.

In this paper, a family of zero voltage switching (ZVS) buck/boost converters with positive common rail (PCRBBC) is proposed for the PMSM sensorless driving system in electric vehicles. The proposed family of PCRBBCs includes more than 12 topologies with coupled LC or LD auxiliary circuits. Their special characteristics are the common positive connection between input and output ports, ZVS conditions, and a variety of different topologies to be chosen. The operation principle, soft-switching realization limit, application conditions, design guidance of proposed ZVS PCRBBCs are analyzed. Finally, an experimental prototype is built to verify the correctness and validity of the proposed soft-switching topologies.

In this paper, a multi-objective optimization strategy is proposed for the design of high-density low-noise motors. The approach considers efficiency and computational accuracy and uses a wide-frequency-domain multi-operating-condition electromagnetic vibration source as the objective function. The first step is to identify the wide-speed multi-operating-condition vibration source of the motor using the unit-force-wave response method. Then, a multi-objective optimization model of high-density low-noise motors is established by combining electromagnetic design objectives to create a mapping relationship between the electromagnetic noise source and the structural parameters. This method optimizes a 48-slot 8-pole IPMSM for suppression in electric vehicles. The amplitude of the vibration source of the prototype is reduced by 80.73% and 85.48%, respectively, while the average torque remains unchanged. The vibration acceleration of the motor is significantly suppressed under the wide frequency domain multi-operating conditions. This paper provides technical support and design references for engineering applications.

This brief presents a fully integrated automatic impedance-matching RF energy harvesting system that automatically compensates for variations at the antenna-rectifier interface. The control loop is fully integrated on-chip with a low-voltage, low-power design. The design is fabricated in 0.18-μm CMOS technology, and the active chip area is 0.064 mm². The sensitivity optimized by impedance tuning can be improved to more than -30.5 dBm for 0.7 V output at varied initial mismatches, leading to a maximum increase in sensitivity of 5 dB. The control circuit's power consumption is only 2.4 nW, and the minimum supply voltage is 416 mV.

This paper presents a 2: 1 analog multiplexer (AMUX) using IHP’s 130-nm SiGe BiCMOS process. The proposed AMUX expands the analog bandwidth (BW) of CMOS-based DACs by introducing interleaving sampling technique, thus improving the data rate of single lane in modern optical communication systems. Meanwhile, a detailed analysis of process selection which particularly focuses on material and device considerations is adopted, and a principle of the BW expansion is comprehensively discussed. The AMUX exhibits a BW >70 GHz, achieving a data rate of 200 Gb/s under PAM-4 modulation.

An application dependent FPGA interconnect testing scheme is presented. The goal is to reduce the number of test configurations while keeping high fault coverage. Reduction is done by using SMT constraints that allow multiple nets as a group to use one input vector, so that the number of test configurations is reduced. Based on the complete fault model, a novel approach to generate SAT formulas, most notably dominant bridging faults, are explained to retain coverage. Experiments on FPGAs shown that this method yield on average 44% fewer configurations on circuits with 1000∼100000 LUTs comparing with existing methods, with full fault coverage.

Due to the low noise and high linearity characteristics of GaAs Hetero-junction Bipolar Transistors (HBTs), Low Noise Amplifiers (LNAs) are widely used in aerospace, communication, computer, and other fields. Extracting device model parameters is of great significance for subsequent research on the electromagnetic compatibility characteristics of such devices. In this paper, based on the small signal model, the model parameters of the amplifier are extracted by combining the I-V characteristics of the amplifier under different external voltage conditions. The linear model parameters are extracted using a fitting analysis method to obtain the Pspice circuit model of the GaAs amplifier under normal operating conditions. The simulation results align closely with the measured results. Compared with traditional modeling methods, this approach effectively resolves the issue of being unable to measure parameters due to chip packaging. This method holds substantial significance in extracting circuit model parameters and conducting in-depth research on circuit electromagnetic compatibility characteristics of this device.

This paper presents a bandgap reference (BGR) circuit with high precision and low power, which is suitable for wide supply and temperature range DC-DC converters. A thermal compensation method is designed to improve output accuracy. A thermal shutdown detection (TSD) circuit is proposed to prevent overheating. It also adopts a two-channel pre-regulator, which reduces the current consumption and area while enhancing PSRR. The measured results show the temperature coefficient (TC) stands at 5.69 ppm/°C in the range of -40°C to 155°C. The typical current consumption is 0.84μA in the supply range from 3.5 to 40 V. The PSRR is -86dB at 1kHz.

A wideband crossed dipole antenna for dual-polarized applications is presented in this paper. The antenna consists of a printed crossed dipole radiator loaded with periodic slots, four metal posts, four metal sidewalls and a metal reflector. The crossed dipole antenna is directly fed by a simple coaxial cable, achieving stable dual-polarization radiation characteristics. Here, two approaches are adopted to adjust the high and low resonant frequency of the antenna with large freedom. Firstly, four metal posts are introduced into conventional crossed dipole antenna, and their distance from the feeding point can independently adjust the lower resonant mode. Secondly, periodic slots are etched on the crossed dipole arms, and the upper resonant frequency can be controlled independently by altering the length of these slots. Also, the metal sidewalls on the ground are used herein to obtain enhanced gain property. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The measured results show good performance of a relative bandwidth of 64.3% for VSWR ≤ 2 (1.32-2.57 GHz). Moreover, the antenna has good unidirectional radiation performance and can achieve maximum gain of 9.1 dBi at 2.3 GHz.

In order to solve the problems of the traditional model reference adaptive system (MRAS) speed estimation adaptive mechanism, such as poor tracking accuracy and slow response, A new dual sliding mode adaptive observer is designed to estimate the rotational speed and rotor position of permanent magnet synchronous motor (PMSM). Firstly, a new two-variable complex reaching law is used to replace the traditional first-order sliding mode for velocity loop control, and an anti-saturation scheme is introduced to improve the anti-interference ability of the system. Secondly, the PI adaptive mechanism in the traditional MRAS is replaced by a new super-twisting weighted integral type algorithm adaptive observer (STWITA-AO), which effectively speeds up the convergence of the estimated speed and reduces the inherent chattering of the sliding mode structure. Finally, the relevant simulation is compared and verified. The simulation results show that the estimation strategy based on the new double sliding mode MRAS control can make the speed estimate converge to the actual value faster, and improve the dynamic performance and robustness of the observer.

The novel rare earth variable flux permanent magnet synchronous motor (PMSM) for electric vehicles is proposed. The structure and magnetic field regulation characteristics are analyzed, the variation of magnetic density, no-load back electromagnetic force and output torque with speed was studied through finite element simulation. The weak magnetic field expansion speed performance of the novel PMSM has been verified through experimental equipment. The adjustable electromagnetic field with running speed on the rare earth PMSM increases the high-speed operation range of vehicle.

A wideband dual-line polarized antenna with low-profile property is presented in this paper. The dual-polarized antenna consists of two crossed antenna elements over a metal reflector and is excited by RF connectors vertically. Here, the crossed antenna element is based on Vivaldi radiator to obtain wideband performance. By loading resistors on the patches of Vivaldi radiator, not only the impedance matching of the proposed antenna can be improved further but also the profile is reduced greatly. Whatever, the loaded resistors can also depress radiation efficiency of the antenna element to a certain extent, especially in the lower band. For this reason, three periodic slots etched on the Vivaldi radiator are introduced herein to enhance the gain performance. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The results show good performance of a relative bandwidth of 153% for VSWR ≤ 2 (2-15 GHz) and a low profile of 0.22 λ_L (in terms of the lowest frequency of the band). Besides, the prototype can achieve an average gain of approximately 5 dBi and a maximum radiation efficiency of 80% within passband.

Level-increased nearest level modulation (NLM) has been widely used in the modular multilevel converter (MMC) due to its simple implementation and low switching frequency in recent years. However, there are some disadvantages such as the poor performance of output voltage distortion and harmonic circulating current. A harmonic circulating current (CC) suppression method based on level-increased NLM is proposed in this paper. The impact of level-increased NLM on the CC is firstly analyzed. Then, a 5-voltage-level compensation method for harmonic CC suppression is proposed. Simulation and experiment verify the effectiveness of the proposed method.

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( f_T). Broadband operation is achieved using an enhanced degenerated Darlington f_T-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional f_T-doubler structures, the enhanced cascode Darlington f_T-doubler structure reduces the “V_CE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher V_CE for amplifying transistors, which represents higher f_T,_peak performance. Benefiting from the proposed Darlington f_T-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181- f_T bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

To improve the dynamic response performance and robustness of a permanent magnet linear synchronous motor (PMLSM)-based servo system, an adaptive proportional-integral-derivative (PID) controller based on a particle swarm optimization neural network is proposed. First, according to the mechanical dynamics equation of the PMLSM, a mathematical model of the PMLSM was established. Second, an adaptive PID speed controller is designed to realize real-time control of the PMLSM. To improve the dynamic performance and stability of the controller, a particle swarm optimization neural network is used to dynamically tune the parameters. Finally, the effectiveness of the proposed controller was verified on the MATLAB/Simulink simulation platform. Compared to the traditional PID controller, the adaptive PID controller can improve the dynamic performance of the system more effectively.

A novel buck-boost power converter is proposed to improve the performance of switched reluctance generator (SRG) system in an electric vehicle. In the proposed topology, the energy conversion part is formed by a buck-boost circuit and additional switches, with which, it is flexible to significantly boost the magnetization voltage and demagnetization voltage, thereby the output power range is improved and the power losses are reduced. The basic structure of the proposed converter is presented first and the attached operating modes are analyzed. The control strategy of the SRG system is then made to control the output voltage and the boost capacitor voltage. The simulation results show that compared to the conventional buck-boost converter, the proposed converter enhances the efficiency and reduces the power losses.

How to replace the referee in sports with artificial intelligence has attacked a huge amount of attention recently. In this paper, non-battery pressure detection and communication system are designed and fabricated aiming to help the referee in the basketball games. To get the information from player and ball at the same time, the designed system is consisted of three parts, including the basketball monitoring system, the shoes monitoring system, and the laptop to collect and process the data. For the basketball monitoring system, eight piezoelectric polyvinylidene fluoride (PVDF) flexible thin films are used as the sensor on the surface of the basketball with the sensitivity of 0.065 V/N and four hard piezoelectric Lead Zirconium titanite (PZT) patches are set inside the ball as the power source. As for the shoes monitoring system, four PZT patches work as both power source and pressure sensor with a sensitivity of 0.025 V/N. To solve the referee problem in basketball game, time delay of different systems is first measured. The different systems have similar time delay of about 3s, which will help to make sure whether the players break the rules. In this paper, whether the player has a traveling violation in a game can be refereed by the collected data, which has more than 97% accuracy. This work shows an innovative progress in automatic referees in games and the Internet of Things (IoT) in the human health monitoring.

Approximate computing has excellent result in error-tolerant applications sacrificing computational accuracy for better performance in the area, speed, and power consumption. As the most basic operation, addition is used in a large number of applications in various occasions. Therefore it is of great importance to optimize the performance of addition computation. In this paper, a segemented carry prediction adder (SCPA) structure is proposed, which splits the long carry chain into several short chains for parallel computation. The design parameters are diversified by adjusting the size of the blocks and the prediction depth of each subadditive to achieve different levels of performance. Flexible parameter tuning allows different design goals to be achieved based on specific performance requirements, which makes SCPA a useful design guideline for approximate adders. The error performance of SCPA is mesured by MRED, NMRED, ER, and other indicators and significantly has the best statiscal performace compared to similar designs. The proposed design is synthesized under TSMC 65nm process, and the result shows that the SCPA has a very nice accuracy-power tradeoff under 8-bit and 16-bit condition.

Transient execution attack does not affect the state of processor microarchitecture, which breaks the traditional definition of correct execution. It not only brings great challenges to the industrial product security, but also opens up a new research direction for the academic community. This paper proposes a defense mechanism for SMT processors against launching transient execution attacks using shared cache. The main structure includes two parts, a security shadow label and a transient execution cache. In the face of the side channel attacks widely used by transient execution attack, our defense mechanism adds a security shadow label to the memory request from the thread with high security requirement, so that the shared cache can distinguish the cache requests from different security level threads. At the same time, based on the record of security shadow label, the transient execution cache is used to preserve the historical data, so as to realize the repair of the cache state and prevent the modification of the cache state by misspeculated path from being exploited by attackers. Finally, the cache state is successfully guaranteed to be invisible to any attacker’s cache operations. This design only needs one operation similar to the normal memory access, thus reducing the memory access pressure. Compared with the existing defense schemes, our scheme can effectively prevent Spectre attack, and the overhead of performance is only 3.9%.