IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Advance online publication
Displaying 1-23 of 23 articles from this issue
  • Wenyu Ma, Wenquan Cao, Yixin Tong, Bangning Zhang
    Subject Area: Microwave and millimeter wave devices, circuits, and modules
    Article ID: 19.20220184
    Published: 2022
    Advance online publication: May 25, 2022
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    A slot antenna array backed by substrate integrated waveguide (SIW) cavity with high gain, wideband and low sidelobe levels (SLLs) is proposed in this letter. Four 2 × 2 slots antenna elements based on SIW cavity are used as the radiation structure. A broadband SIW corporate-feed network is equipped on the bottom layer to feed antenna array. Due to the broadband characteristics of antenna element and feed network, antenna array with wide band is obtained. Then, through the dislocation distribution of antenna elements, the SLLs of antenna array can get greatly reduced. A prototype has been fabricated using standard PCB process, and measured for verification. As for the measurement results, the impedance bandwidth below -10 dB is from 18.2 GHz to 21.7 GHz (17.5%). The maximum gain is 17.4 dBi at 20.5 GHz. Most importantly, the SLLs of both E- and H-plane are all lower than -15 dB in the working band.

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  • Akira Tanaka, Yasuhiro Okamura, Atsushi Takada
    Subject Area: Optical hardware
    Article ID: 19.20220196
    Published: 2022
    Advance online publication: May 25, 2022
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    In this letter, we numerically investigate noise suppression using self-phase-modulation (SPM) in transmission optical fiber and degenerate phase-sensitive optical amplifier (PSA). It is clarified that the optimum fiber input signal power for SPM and phase shift for amplitude noise suppression of 10 Gbit/s binary-phase-shift keyed (BPSK) signals. Then, 10-Gbit/s BPSK signal transmission on multi-relay systems is evaluated. When the fiber input optical power is 5 mW, the signal-to-noise ratio (SNR) of PSA output is larger than 20 dB on 200-relays while SNR of the conventional PSA output is 15 dB after 63-relays.

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  • Jianhua Deng, Yanping Wang
    Subject Area: Power devices and circuits
    Article ID: 19.20220165
    Published: 2022
    Advance online publication: May 19, 2022
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    When the photovoltaic system is put into use, some natural objects will cause partial shadows on the photovoltaic modules. And in this case, the output characteristics of the photovoltaic array will change from the original "single peak" to "multi-peak", and the power of the photovoltaic array will have multiple extreme values, which will increase the difficulty of tracking the maximum power of the photovoltaic array. The traditional maximum power point tracking (MPPT) algorithm is no longer applicable. Most of them fall into the local maximum power and cannot find the global maximum power. Although the particle swarm optimization algorithm (PSO) has a certain ability to solve the global optimization problem, the standard particle swarm optimization algorithm can’t be regarded as a complete global optimization algorithm. Since the power output curve of the photovoltaic array is severely non-linear in the shaded situation, the standard particle swarm optimization algorithm may also fall into a local optimum and fail to find the global optimum. Compared with the standard particle swarm optimization algorithm, the particle swarm optimization algorithm with time-varying compression factor proposed in this paper can better balance the relationship between global search and local search, and can effectively avoid falling into the local optimal value and not finding it. To the correct maximum power point, while also increasing the speed of convergence. Comparing the method proposed in this paper with the standard particle swarm algorithm through experiments, the results show that the method proposed in this paper is of great significance for improving the efficiency of photovoltaic systems under partial shadow conditions.

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  • Junjun Qiu, Bangan Liu, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada
    Subject Area: Integrated circuits
    Article ID: 19.20220201
    Published: 2022
    Advance online publication: May 17, 2022
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    This paper proposed a digital synthesizable GMSK receiver baseband circuit for the Sub-GHz transceiver. The proposed digital baseband(DBB) circuit is composed of carrier recover, timing recovery, and demodulation blocks. An improved polarity Costas-loop with integration and dump(IP) is proposed for carrier frequency recovery. Timing recovery is based on the interpolation and Gardner error detection methods to determine the optimal sampling time. The proposed DBB is fabricated in 65nm CMOS technology. It realizes less than 10-6 bit error rate(BER) at 14dB Eb/N0 environment, with 314 µW power consumption in the measurement.

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  • Si-Shik Jeon, Jong Man Joung, Chun-Kwon Lee, Young-Dal Kim
    Subject Area: Electromagnetic theory
    Article ID: 19.20220113
    Published: 2022
    Advance online publication: May 16, 2022
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    The distribution cable may be considered the most critical element for power system operation through the key functions of electricity supplement and control and instrumentation signal transmission. Hence, there is a growing need for cable diagnostic techniques that enable accurate condition monitoring and fault detection in cables where external artifact signals are to be continuously measured. This research presents a technique for detecting cable faults based on autoencoder regression-based reflectometry with multiple frequency sinusoidal signals. Estimations of the reflected signal and preliminary test results of a non-faulty cable are used to train the time-series signal reconstruction and anomaly detection, allowing the distinguishment between a fault-induced reflected signal and various artifacts resulting from noise, input mismatch, or other factors. Experiment results on fault location in bypass cable and the reflected signal discrimination on branched network cable have validated the usefulness of the proposed algorithm.

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  • Fengjuan Wang, Quan Peng, Ningmei Yu, Yuan Yang
    Subject Area: Electron devices, circuits and modules
    Article ID: 19.20220187
    Published: 2022
    Advance online publication: May 16, 2022
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    The three-dimensional integration technology based on TSV can greatly improve the miniaturization of passive components. In this paper, a three-dimensional substrate integrated waveguide (SIW) filter suitable for 105GHz-110GHz is proposed. By using the coupling matrix synthesis method, a SIW filter is proposed with good high frequency performance and small volume. The results show that, the center frequency is 107GHz, the insertion loss is less than 1.5dB, the return loss is more than 20dB, and its physical size is only 0.7028 × 1.2428mm2

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  • Yoshinao Mizugaki, Naonori Sega, Hiroshi Shimada
    Subject Area: Superconducting electronics
    Article ID: 19.20220194
    Published: 2022
    Advance online publication: May 16, 2022
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    We designed and operated a 4-bit single-flux-quantum pulse-frequency modulator for bipolar D/A conversion. It was based on our previously-proposed “sum of selected bit sequence” configuration. Two functions, a synchronization scheme with a reference signal source and a complement number system for realization of bipolar output voltage, were implemented. A test circuit excluding the output analog stage (dual double-flux-quantum amplifier) was fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. The synchronization function was evaluated in terms of the average voltages, which agreed well with the expected values. The bipolar D/A conversion was successfully emulated by using the positive and negative output signals. The maximum over-biased input voltage was determined to be 230 µV, of which the corresponding SFQ repetition frequency was 111 GHz.

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  • Haohan Yang, Heng You, Shushan Qiao
    Subject Area: Integrated circuits
    Article ID: 19.20220157
    Published: 2022
    Advance online publication: May 11, 2022
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    An efficiency-enhanced fully integrated power amplifier (PA) for wireless local area networks (WLANs) was implemented based on the GaAs heterojunction bipolar transistor (HBT) process. A harmonic tuning network that can absorb the parasitic inductance of the bonding wires is proposed, which reduces the chip area significantly. The network provides nearly optimum fundamental and second harmonic impedances from 5.0 to 5.5 GHz. Additionally, a novel adaptive bias circuit that corrects the AM-AM and AM-PM distortion and improve thermal stability at high input power was proposed. With a chip dimension of only 1.06 mm2, the PA achieves a gain of 31.1-31.6 dB and saturated power of 29.9-30.3 dBm with a peak power-added efficiency (PAE) of 49.3%-51.8% across 5.0-5.5 GHz. The PA also shows an output power of 22.1 dBm (EVM=-32 dB) with 18.4% PAE under an 802.11ac MCS9 VHT160 test signal. In addition, the PA delivers 17.5 dBm (EVM=-42 dB) output power when tested with the 802.11ax MCS11 VHT160 signal at 5.25 GHz.

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  • Zhi Li, Huidong Zhao, Jialu Yin, Shushan Qiao, Yumei Zhou
    Subject Area: Integrated circuits
    Article ID: 19.20220102
    Published: 2022
    Advance online publication: May 09, 2022
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    A fully integrated CMOS RC oscillator is presented. The oscillator is inverter-based. An adaptive body biasing(ABB) scheme is proposed to regulate the trip point of the decision inverter adaptively, thus alleviating the frequency variation over PVT. To achieve low power consumption all components are in the sub-threshold region. The circuit is designed in a 55-nm CMOS process with an area of 0.052 mm2. The simulation result shows a temperature sensitivity of 59 ppm/℃ from -40∼125℃ which achieves a 72 ppm/℃ reduction as compared to an oscillator without ABB. the oscillator operates at 33kHz and consumes 183 nW from a 0.6V supply.

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  • Zhaojie Dong, Lan Chen, Ying Li
    Subject Area: Integrated circuits
    Article ID: 19.20220167
    Published: 2022
    Advance online publication: May 09, 2022
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    Existing functional validation approaches and post-manufacturing tests are inadequate to detect all hardware bugs and hardware Trojans in third-party intellectual property blocks (3PIPs). Especially for cryptographic IPs, a well-designed framework is needed for detecting and mitigating hardware security risks even after chip deployment. In this paper, we present an innovative multi-level architecture providing runtime hardware security detection and response. The proposed architecture consists of a controller and a security wrapper, enabling the collaborative operation of three different types of detection and three levels of response according to the potential malicious impact. We show that a field programmable gate array prototype of the proposed architecture can pursue 4 hardware bug and 6 hardware Trojan detection towards an AES IP, and make appropriate protective responses.

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  • Xiangcheng Liu, Yingyu Chen, Zhangwen Tang
    Subject Area: Integrated circuits
    Article ID: 19.20220180
    Published: 2022
    Advance online publication: May 06, 2022
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    This paper presents a process, voltage, and temperature (PVT)-insensitive high dynamic range output stage for switched-capacitor (SC) circuits. A new technique of constant threshold voltages using bulk voltages adjustment is presented to realize the output stage with the N and P-type (N-P) complementary transistors. Boosting circuits are used to generate bulk voltages higher than the supply voltage or lower than the ground voltage. The stability of the bulk loop consisting of a boosting circuit, an amplifier, and a replica transistor is studied. This design is implemented in TSMC 0.18µm technology. Simulation results show that the output stage can achieve a differential dynamic range of 2.5Vpp, obtaining a significant 47% improvement.

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  • Ivan Padilla-Cantoya, Marco A. Gurrola-Navarro, Carlos A. Bonilla-Barr ...
    Subject Area: Integrated circuits
    Article ID: 19.20220130
    Published: 2022
    Advance online publication: April 27, 2022
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    A four-quadrant analog multiplier with ultra-low supply voltage operation, rail-to-rail input swing and insensitive to different dc levels between the multiplied input signals is presented. It is based on the Floating-Bulk technique, in which the input signal is coupled to the bulk terminal of a PMOS transistor by means of an input capacitor. This allows rail-to-rail operation and eliminates the dc level of the input signals regardless of the offset between them, maintaining linearity. Moreover, it also eliminates the threshold-voltage requirement in the signal path of the input transistors, allowing very low voltage operation defined by a gate-source and a drain-source voltages. Experimental results in 0.5µm technology demonstrate rail-to-rail operation with a 1.1 V supply voltage even with different dc level voltages between the multiplied input signals. It offers a distortion of THD = 0.95 % for an input signal of 0.2Vpp at 100kHz.

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  • Peiyong Zhang, Yuquan Su, Yike Li, Kaitian Huang
    Subject Area: Integrated circuits
    Article ID: 19.20220163
    Published: 2022
    Advance online publication: April 25, 2022
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    Arc faults in power systems may cause significant damage to equipment and even lead to electrical fires and hazard for personnel if they are not detected and isolated promptly. The series arc fault in a distribution system can be more dangerous compared to the parallel arc fault, because its low fault current will hinder the circuit breakers from responding in a timely manner. Therefore, it is necessary to properly detect the series arc fault. In this paper, a system-on-chip (SoC) for series AC arc fault acquisition is presented, which is based on two channels of configurable sampling rate successive approximation register (SAR) analog-to-digital-converters (ADCs). As the arc faults with different loads have different characteristics and may need a higher sampling rate under some circumstances, the adjustable sampling rate can meet varying needs. The system is implemented using a 55 nm CMOS process with a die area of 4.683 mm2 and power dissipation of 75.9 mW. The proposed SAR ADC design can achieve a good Schreier figure-of-merit (FoM) of 161 dB at 1 MS/s sampling rate. With this ADC design, the SoC can complete arc faults acquisition with high precision and configurable sampling rate at a low cost. Meanwhile, the system can sample voltage and current signals from the smart grid respectively to initially locate the arc fault.

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  • Kwon Sang Wook, Yong Seo Koo
    Subject Area: Electron devices, circuits and modules
    Article ID: 19.20220110
    Published: 2022
    Advance online publication: April 19, 2022
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    External capacitors in conventional LDO regulators can reduce transient response characteristics such as overshoot and undershoot. However, the capacitor-less LDO regulator proposed in this study achieves the transient response improved by applying body technique to the pass transistor, thereby provides the high areal efficiency and excellent current driving capability, and shows the improved ESD robustness characteristics. Also, the proposed ESD protection device based on due to the SCR (Silicon Control Rectifier) built into the output node and the power line. As a result, it was confirmed that the transient response characteristics of the proposed LDO regulator were improved and free space could be secured by applying the body technique of the pass transistor. The operating conditions of the proposed LDO regulator were set as an input voltage varying from 3.3V to 4.5V, a maximum load current of 200mA, and the output voltage of 3V. As a result of the measurement, when the load current was 200mA, the voltage was found to be 23 mV in the undershoot state and 29 mV in the overshoot state. In addition, the ESD robustness characteristic of HBM is secured at 8kV or higher.

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  • Xiaoqiang ZHANG, Lan TANG, Xinggan ZHANG, Xinxing ZHENG, Mingyu XU, Fa ...
    Subject Area: Integrated circuits
    Article ID: 19.20220154
    Published: 2022
    Advance online publication: April 19, 2022
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    In this paper, a low delay circuit structure is proposed for composite field S-box circuit. In the low delay structure, the multiplications over GF((22)2) are constructed by XOR-AND-XOR-networks, and the multiplicative inverse over GF((22)2) are constructed by AND-XOR-networks. As XOR-networks are linear operations, they can be further expressed as constant matrix multiplications. In this paper, the adjacent matrix multiplications in S-box are merged to reduce the delay. Compared with previous works, our S-box implementations have lower delay.

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  • Ying Chen, Jun Li, Fei Ding, Liqiang Cao
    Subject Area: Microwave and millimeter wave devices, circuit, and hardware
    Article ID: 19.20220122
    Published: 2022
    Advance online publication: March 25, 2022
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    Due to the advantages of good thermal and electrical performance, lower cost, greater design flexibility, fan-out wafer-level package(FOWLP) has been widely used in millimeter-wave applications. In this letter, a fan-out wafer-level package with the size of 12mm×12mm for the millimeter-wave applications is accomplished by the redistribution layer first(RDL-First) process. The double-sided multiple redistribution layers(RDLs) are used to fan out the signals and to form the antenna-in-package(AiP). An antenna integration scheme for the Ultra Short Range automotive Radar(USRR) chips with four transmit and receive channels was achieved. In addition, a 1×3 series fed aperture-coupled antenna array in the fan-out area was designed. Correspondingly, a probe based antenna measurement setup for FOWLP-AiP working in E band was carried out. The measurement results are in good agreement with the simulation.

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  • Yu Liu, Mingliang Chen, Chenge Wang, Jiarui Liu, Zhiyu Wang, Hua Chen, ...
    Subject Area: Integrated circuits
    Article ID: 19.20220084
    Published: 2022
    Advance online publication: March 09, 2022
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    This letter proposes a parasitic elimination bootstrapped switch and a fast settling residual amplifier to be used in multiplying digital-to-analog converter (MDAC) in order to improve the performance of pipelined ADC at high frequency. The parasitic elimination bootstrapped switch improves the sampling spurious free dynamic range (SFDR) by more than 6dB by shielding the nonlinear parasitic capacitance of the MOS transistor substrate. In addition, at high frequency, the negative zero point introduced by the later stage switch-capacitor circuit (which is easy to be ignored) will seriously deteriorates the settling time of residual amplifier in the former stage. A new zero-pole elimination technique is proposed, which greatly reduces the settling time of residual amplifier by nearly 11% and further improve the performance of MDAC. Simulated in 28nm CMOS technology, as the input signal is 1.38GHz, the former stage of the pipelined ADC implements high-speed high-resolution to obtain a SFDR of 75.77dB and a signal-to-noise-plus-distortion ratio (SNDR) of 68.05dB at a sampling frequency of 2.2GS/s.

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  • Jinzhi Lai, Jueping Cai, Jie Chu
    Subject Area: Integrated circuits
    Article ID: 19.20220078
    Published: 2022
    Advance online publication: March 07, 2022
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    Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used for fine-grain flow control and Quality of Service (QoS), yet it is the major contributor of area and power consumption. In this paper, we propose a hybrid buffer design with SRAM and Spin-Torque Transfer Magnetic RAM (STT-RAM) for NoC router leveraging a novel architecture combined Virtual Channel (VC) and Virtual Output Queuing (VOQ) to store congested and uncongested flow separately. Experiments demonstrates that the proposed scheme can achieve 11.8% network performance improvement and 32.9% power saving with only 8.2% area overhead degradation compared to conventional SRAM based buffer design.

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  • Jing Xia, Chengxi Bian, Wa Kong, Yongpeng Zhu, Wence Zhang, Ruijia Liu ...
    Subject Area: Microwave and millimeter-wave devices, circuits, and systems
    Article ID: 19.20220043
    Published: 2022
    Advance online publication: February 24, 2022
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    This paper proposes a filtering matching network optimization design method using the fragment-type structure for continuous inverse class-F (CCF-1) power amplifier (PA). Different from the conventional microstrip matching structure, the fragment-type structure is used to increase the flexibility of optimization for a sharp roll-off at the second harmonic band. By using a multi-objective evolutionary algorithm, a filtering output matching network (OMN) with the fast transition between the passband and stopband is designed and optimized. For verification, a 1.5-3 GHz broadband CCF-1 PA is designed, simulated and measured. Simulated results show that, compared with conventional Chebyshev filtering OMN design, the operational bandwidth of the proposed design can be expanded by about 15%. Experimental results show that measured efficiency of 65%-77% with a corresponding output power of 40.2-42.2 dBm over a fractional bandwidth of 66.7% can be achieved.

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  • Jiazhe Li, Rui Li, Huanting Lu
    Subject Area: Power devices and circuits
    Article ID: 18.20210501
    Published: 2021
    Advance online publication: December 24, 2021
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    This paper introduces a method to achieve fast scanning power supply for Proton Therapy. To meet the specific needs of this power supply, a new structure consists of dynamic module (high voltage part) and static module (low voltage part) has been designed and tested. The simulation results and actual waveform were listed in this paper. The results showed that the current rising slope can reach 90kA/s.

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  • Zhiqiang Wang, Xin Liu, Zhiqiang Li, Xiaosong Wang, Minghua Wang, Quan ...
    Subject Area: Microwave and millimeter wave devices, circuits, and modules
    Article ID: 18.20210286
    Published: 2021
    Advance online publication: November 09, 2021
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    This paper presents a four-way current-combining Ka-band power amplifier(PA) in 65-nm CMOS technology. A symmetrical, transmission line based four-way current combiner, together with output transformers, is used to transfer the high load impedance(4*ZL) to the desired Zopt for each power unit cell. Besides, both interstage/input flexible matching transformers and the power splitter are optimized to improve the performance. Based on the methodology mentioned above, the power amplifier demonstrates a small-signal gain of about 24.12 dB, a saturated output power of 21.56 dBm, and a peak power-added efficiency of 27.3% at 35GHz.

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  • Hao Liu, Ming-Jiang Wang, Ming Liu
    Subject Area: Integrated circuits
    Article ID: 18.20210335
    Published: 2021
    Advance online publication: September 15, 2021
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    Approximate computing has excellent result in error-tolerant applications sacrificing computational accuracy for better performance in the area, speed, and power consumption. As the most basic operation, addition is used in a large number of applications in various occasions. Therefore it is of great importance to optimize the performance of addition computation. In this paper, a segemented carry prediction adder (SCPA) structure is proposed, which splits the long carry chain into several short chains for parallel computation. The design parameters are diversified by adjusting the size of the blocks and the prediction depth of each subadditive to achieve different levels of performance. Flexible parameter tuning allows different design goals to be achieved based on specific performance requirements, which makes SCPA a useful design guideline for approximate adders. The error performance of SCPA is mesured by MRED, NMRED, ER, and other indicators and significantly has the best statiscal performace compared to similar designs. The proposed design is synthesized under TSMC 65nm process, and the result shows that the SCPA has a very nice accuracy-power tradeoff under 8-bit and 16-bit condition.

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  • Xin Jin, Ningmei Yu
    Subject Area: Integrated circuits
    Article ID: 18.20210041
    Published: 2021
    Advance online publication: June 07, 2021
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    Transient execution attack does not affect the state of processor microarchitecture, which breaks the traditional definition of correct execution. It not only brings great challenges to the industrial product security, but also opens up a new research direction for the academic community. This paper proposes a defense mechanism for SMT processors against launching transient execution attacks using shared cache. The main structure includes two parts, a security shadow label and a transient execution cache. In the face of the side channel attacks widely used by transient execution attack, our defense mechanism adds a security shadow label to the memory request from the thread with high security requirement, so that the shared cache can distinguish the cache requests from different security level threads. At the same time, based on the record of security shadow label, the transient execution cache is used to preserve the historical data, so as to realize the repair of the cache state and prevent the modification of the cache state by misspeculated path from being exploited by attackers. Finally, the cache state is successfully guaranteed to be invisible to any attacker’s cache operations. This design only needs one operation similar to the normal memory access, thus reducing the memory access pressure. Compared with the existing defense schemes, our scheme can effectively prevent Spectre attack, and the overhead of performance is only 3.9%.

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