This paper proposes a high-sensitivity G-band detector module based on zero-bias Schottky diodes for direct detection radiometer receivers. To achieve a compact inline configuration with superior performance, the design features a novel U-shaped reduced-height waveguide transition, a cascaded CMRC low-pass filter, and an optimized DC grounding structure. Following rigorous EM-circuit co-simulations, the fabricated module was experimentally characterized. Measurement results demonstrate that the detector achieves a peak voltage responsivity of 9400 V/W in the small-signal regime. Specifically, at the target center frequency of 166 GHz, a high responsivity of approximately 6000 V/W is realized. The detector also exhibits excellent linearity (R² > 0.998) and flatness, validating its suitability for high-performance millimeter-wave sensing applications.

This paper presents a broadband inductor-less CMOS receiver architecture that eliminates on-chip inductors while maintaining wideband impedance matching and acceptable noise performance. The proposed receiver integrates an inductor-less low-noise amplifier (LNA) and an active mixer to achieve compact implementation and reduced parasitic sensitivity; the LNA employs a combined common-gate and common-source topology with a noise-cancellation scheme under a current-reuse configuration, and a modified Gilbert-cell mixer performs single-ended to differential conversion with controllable conversion gain without passive baluns. Designed in a 0.18-µm CMOS technology with a 1.8-V supply, post-layout simulation results demonstrate broadband operation from 0.4 to 2 GHz, achieving a conversion gain of 14.2-17.2 dB and a noise figure of 11.5-13.8 dB with the measurement buffer enabled, while the intrinsic front-end exhibits a minimum noise figure of 6.55 dB. The proposed architecture provides a practical trade-off among bandwidth, noise performance, linearity, and power consumption for highly integrated broadband RF front-end applications.

In this letter, a novel matching network (MN) is proposed for the design of dual-band high-efficiency power amplifiers (PAs). The proposed MN consists of a compact harmonic control network and a fundamental MN integrating series two-section transmission lines, wherein multiple free parameters are introduced to improve design flexibility and expand the parameter solution space. The impedance transformation relationships are analyzed in detail, and explicit design formulas are given for directly solving the circuit parameters. The performance of the fundamental MN is also demonstrated and compared under varying complex load impedances and frequency-ratios. For verification, a 10 W GaN dual-band PA is designed. The measurement results show that the fabricated PA achieves drain efficiencies of 60.5% - 73.7% within the 2.05 - 2.30 GHz band and 65.6% - 76.8% within the 3.35 - 3.75 GHz band. A saturated output power of over 40.3 dBm is achieved in both operating bands.

A novel single-stage lighting-emitting diode (LED) driver based on totem-pole bridgeless boost PFC rectifier and LCC resonant converter is proposed, the two units are integrated together by sharing switches. The totem-pole bridgeless boost PFC rectifier circuit operating in discontinuous conduction mode (DCM), which achieve high power factor. The LCC resonant converter is used here ensures that the primary side switches zero voltage switching (ZVS) and the secondary side diodes zero current switching (ZCS), which both reduce the number of semiconductors and increase the overall efficiency. Finally, a 100W LED prototype is designed, fabricated, and test in the laboratory, the experimental results verify the theoretical prediction.

In recent years, fractional calculus has been used as a novel modeling tool by many converters. This paper studies the modeling of a pseudo-continuous conduction Buck-Boost converter based on the R-L fractional definition and the state-space averaging method. The expressions of DC static operating point, small signal transfer function and inductor current ripple are derived. It is found that compared with the Caputo fractional-order, the DC static operating point of the R-L fractional-order is not only related to the duty cycle, but also affected by the inductance and capacitance order and load. Finally, a fractional order model of PCCM Buck-Boost converter is built to verify the accuracy of the model. The results show that the fractional-order model can describe the operating characteristics of the Buck-Boost converter more accurately.

This paper presents a clock-skew-controlled pipeline optimization method for superconducting rapid single-flux-quantum (RSFQ) circuits. Without changing the circuit’s cell-level topology (netlist connectivity, including the splitter-tree), the pipeline depth along each signal path can be flexibly adjusted by controlling the clock skew between adjacent logic cells. A quantitative relationship between clock skew and latency variation is derived to determine timing configurations at different pipeline depths. A 4-bit adder is designed using cells from the SIMIT Nb03 process library, and a stepwise reduction of its pipeline depth is carried out in simulation to validate the method. At a fixed clock frequency and bias margin, the circuit latency is reduced by 155 ps, while the number of Josephson junctions (JJs) is reduced by about 582.

This paper presents a high Common Mode Transient Immunity (CMTI) modulation circuit for a capacitively coupled gate driver. It proposes an enhanced on-off keying (OOK) transmitter architecture with integrated common-mode (CM) substrate modulation. Through collaboration with the CM interference detection circuit, transmission accuracy and CMTI are improved without additional delay.
Test results show the prototype driver achieves 220 V/ns CMTI, 20 ns propagation delay, the rise and fall times of 10 ns and 12 ns respectively under 15 V supply voltage, and the rise and fall time of 22 ns and 24 ns respectively under 30 V supply voltage with 2.5 MHz frequency and 3.5 nF load.

In this paper, we present the design and fabrication of a 1060-nm single-mode edge-emitting semiconductor laser based on an oxide-confined, surface-grating architecture that simultaneously enables lateral fundamental-mode control, robust longitudinal single-mode operation, and high efficiency with a regrowth-free process flow. Simulations confirm strong overlap of the fundamental mode with the oxide aperture and effective suppression of higher-order lateral modes, consistent with the measured narrow far-field. Under CW operation at room temperature, the device exhibits a low threshold current of 19 mA and a maximum slope efficiency of 0.7 W/A, and it maintains stable lasing at 85℃ with a slope efficiency of 0.64 W/A. A low lateral divergence of 4.2°(FWHM) and a side-mode suppression ratio of 38 dB further demonstrate excellent beam quality and spectral purity.

In low-voltage differential signaling (LVDS) transmitters, data transfer between the core and I/O voltage domains across a large supply voltage difference requires high-speed and low-power level shifters (LSs). This paper proposes a level shifter (LS) that combines cross-coupled and improved current-mirror topologies to address the issues of current contention in the cross-coupled level shifter (CCLS) and limited swing in the current-mirror level shifter (CMLS). In the proposed LS, the improved CMLS branch employs an active-inductor structure and an auxiliary pull-up transistor to accelerate conversion, whereas current-limiting transistors inserted in the CCLS branch further reduce current contention. Implemented in a 55-nm technology, the proposed LS achieves 1.2 V-to-3.3 V level conversion at 800 MHz input frequency with a propagation delay of 249 ps and a dynamic power of 1.84 mW.

This paper presents a background calibration technique that employs ramp signals with different slopes to simultaneously correct timing skew and buffer-induced harmonic distortion in time-interleaved analog-to-digital converters (TI-ADCs). During harmonic distortion calibration, a slow ramp is applied to the input buffer, and nonlinear coefficients are extracted from its transfer characteristics. These coefficients enable accurate digital-domain compensation without degrading the quality of the input signal. For skew calibration, a steep ramp is introduced to detect timing mismatches, providing an input-independent solution that imposes no constraints on the input signal. Furthermore, it avoids periodic variations in input impedance and prevents the generation of additional spurious tones. A 2.5-GS/s 12-bit TI-ADC behavioral model combined with transistor-level front-end circuits is developed to validate the proposed methods. Simulation results show significant improvements in SFDR across the entire frequency range, with skew-induced spurs effectively removed and harmonic distortion greatly suppressed.

A high-frequency reference clock (CK_REF) adopted in charge-pump-based phase-locked loops (CPPLLs) can reduce the feedback division factor, thereby alleviating the noise influence from the phase/frequency detector (PFD), charge pump (CP), and loop filter (LF). However, the PFD, serving as the front end of CPPLLs, suffers from an enlarged blind zone (BZ) that consequently reduces its average gain (K_PFD) during high-frequency operation. To address this issue, this work proposes two pulsed-latch-based PFDs (PLPFDs) that mitigate the BZ and enhance K_PFD. Through analysis of the relationship between the clock frequency (f_CK), the reset loop delay, and the pulsewidth of the clock signal, these two PLPFDs can operate in either a higher-f_CK mode or a lower-BZ mode, depending on whether pulse generators (PGs) are used. Implemented using a 0.18-μm CMOS process, HSPICE simulation results demonstrate an operating frequency range of 1.8-3.4 GHz with lower power consumption in the higher-f_CK mode, and 0.5-1.7 GHz with a minimized BZ of 0.010-0.027 π in the lower-BZ mode. In particular, these PLPFDs can be readily integrated into CPPLLs that employ various high-frequency CK_REF, enabling fast acquisition for advanced communication systems.

This study investigates the radiation mechanism of magneto-electric (ME) dipole antennas through characteristic mode analysis (CMA). Two distinct resonance modes responsible for the formation of dual resonance points are identified. Furthermore, an analytical investigation on wide dipole antennas is performed, leading to the realization of a perfectly complementary radiation pattern with a maximum front-to-back ratio (FTBR) of 40.16dB. The proposed theoretical framework is further validated through its implementation in ME dipole antennas with more complex structures at mmWave bands. This study innovatively advances the current theoretical framework and provides guidance for future design and optimization of ME antenna.

A new permanent magnet linear generator (PMLG) for oscillating buoy wave energy converter (WEC) is proposed in this paper. Compared to traditional machines, this generator focuses on e enhancing the waveform and amplitude of the output voltage of wave energy generators. A detailed explanation of the operating principle, magnetic flux distribution, no-load characteristics, and load characteristics of the generator through analytical modeling and finite element analysis is provided. In the parametric analysis, the effects of different parameters on the no-load electromotive force are calculated to determine the optimal setting parameters. The simulation results demonstrate a significant improvement in the output voltage quality, expanding the effective operating range of the oscillating buoy-based power generation system and enhancing its efficiency. Moreover, by optimizing the input voltage, the design requirements for subsequent power conversion stages can be relaxed.

This letter introduces a method to optimize the temperature offset drift and noise efficiency factor (NEF) for chopper and auto-zero instrumentation amplifiers. In order to optimize offset drift and NEF, our proposed amplifier exploits a threshold voltage (V_th) tracking reference. A prototype of the proposed amplifier was fabricated using a standard 0.35μm complementary metal oxide semiconductor technology and occupies 0.174 mm². Using the Vth tracking reference, an offset drift of 80 nV/℃ is achieved. The measured NEF was 2.45 with a supply current of 1.1 mA.

This paper proposes a cooperative strategy that combines virtual DC signal injection maximum torque per ampere (MTPA) with proportional–integral–resonant (PIR) control to mitigate the torque ripple of interior permanent magnet synchronous machines (IPMSMs) caused by inverter nonlinearity. The virtual DC signal is superimposed on the d–q-axis feedback currents to track the optimal current angle accurately, while a PIR controller provides high-gain compensation at the 5th and 7th harmonic frequencies, significantly improving current waveform quality. Experimental results demonstrate that, compared with conventional MTPA and MTPA with virtual signal injection only, the proposed scheme achieves the lowest torque ripple and total harmonic distortion (THD) of the phase current, and realizes higher-precision MTPA operation with a smaller current magnitude under identical load conditions.

This article aims to improve the simplicity, speed, and accuracy of the resonance frequency identification algorithm. First, a brief introduction to the resonance of magnetic-geared motors (MGM) is provided. Then, a simple and more easily implementable identification method combining the second order generalized integrator and frequency locked loop (SOGI-FLL) is introduced. Based on this, to reduce convergence time and increase control degrees of freedom, an improved second order generalized integrator-frequency locked loop (ISOGI-FLL) identification algorithm is proposed, and its performance is analyzed. Finally, the effectiveness of the proposed algorithm is validated through experiments.

This paper presents an autonomous bias-flip rectifier (BFR) integrated with an on-chip flip switch timing controller (FSTC) designed for piezoelectric energy harvesting. The proposed FSTC utilizes a pulse-width modulation (PWM)-based feedback loop that automatically calibrates the switch control pulse width, thereby eliminating the need for post-fabrication trimming and allowing the circuit to adapt to component variations. Implemented in a 0.18-μm CMOS process, the circuit achieves fully autonomous operation and can successfully cold-start from a piezoelectric harvester’s open-circuit voltage of 2 V. Measurement results confirm that the FSTC effectively optimizes the bias-flip timing, thereby maximizing the harvested power. Compared to an ideal full-bridge rectifier (FBR), the proposed BFR achieves up to 3.2× higher output power. These results demonstrate the effectiveness of the proposed on-chip automatic calibration architecture in realizing high-efficiency and cost-effective vibration energy harvesting systems.

To address the challenge of real-time and accurate identification of mutual inductance and load parameters in LCL-LCL-type magnetically coupled wireless power transfer (MC-WPT) systems, this paper proposes a parameter identification method based on a Fully Connected Network (FCN). By establishing the electrical model of the LCL-LCL-type MC-WPT system and constructing a high-dimensional simulation dataset, the FCN is utilized to achieve a high-precision nonlinear mapping between the system’s electrical quantities and the mutual inductance/load parameters. This method enables fast prediction and estimation of parameters, featuring advantages such as a simple structure, high computational efficiency, and ease of engineering implementation. Simulation and experimental results demonstrate that the proposed FCN identification model constrains the identification errors of mutual inductance and load parameters within 2.5%, while requiring minimal computational resources and achieving fast identification speed. The research findings can provide effective technical support for the online parameter identification of MC-WPT systems.

Traditional LLC converters suffer from efficiency degradation and load-dependent voltage regulation when operating off-resonance for wide output ranges. This paper proposes a dual-mode secondary-side modulated LLC topology. The primary side switches between Dual Full-Bridge (DFB) and Dual Half-Bridge (DHB) modes, significantly widening the output voltage range. Simple secondary-side PWM modulation achieves load-independent regulation and maintains ZVS operation at the resonant frequency for high efficiency. A PI-BPNN smooth transition strategy is introduced to mitigate voltage overshoot during mode switching. A 195 V input, 48.75-390 V output prototype validates the converter's advantages and the control strategy's effectiveness.

A practical copper-tape-based impedance matching circuit for helical antennas is presented, utilizing a Klopfenstein taper. The design uses standard acrylic cylinders and adhesive copper tape for low-cost fabrication without complex internal structures. The antenna achieves S₁₁ < -10dB from 3.8 to 6.4GHz, covering the 5.65-5.85GHz range, with stable reflection coefficient characteristics. The insertion loss of the matching section was experimentally evaluated using a two-antenna method based on the Friis transmission equation, and was found to be less than 0.15dB per matching section in the target operating band. This approach demonstrates a reproducible and low-loss matching technique suitable for microwave axial-mode helical antennas.

A compact monopole antenna designed for triple-band functionality in multiple application networks is proposed. This antenna simply contains a pair of antisymmetric L-shaped branches and is constructed on FR4 substrate, which occupies only a miniature volume of 10×20×1.6 mm³. By properly designing the branches based on multiple harmonic resonance, three impedance bands including 2.35-2.7, 3.3-3.7, 5.05-9 GHz can be completed with this antenna. The antenna's resonant characteristics can be easily adjusted by changing the lengths and widths of its branches. With a compacted size and suitable radiation performance, the suggested monopole antenna may well work as an internal antenna for LTE/Wlan/Wimax/5G NR/V2X/WiFi 7 band wireless applications.

This study proposes a topology optimization approach to reduce current imbalance in a power module with multi parallel-connected devices. In this study, the conductor layout is derived by a density-based topology optimization that minimizes the coefficient of variation (CV) of the device currents under constraints for grayscale suppression, open/short-circuit prevention, and preservation of the total current. In the optimized results with 12 parallel devices, several disconnections occurred when open/short circuit prevention and the binarization term were not applied. By incorporating both methods, the optimized layout maintained proper connection and reduced current imbalance.

Finite field inversion is a fundamental operation in cryptographic systems, particularly in Elliptic Curve Cryptography (ECC). The Itoh-Tsujii Algorithm (ITA) is a prevalent method for efficient inversion in hardware implementations within binary extension fields. This paper introduces an optimized parallel architecture for ITA that reduces computation time by minimizing clock cycles while maintaining a balanced trade-off in delay and area utilization. Our approach leverages a Hex-ITA framework in GF(2²³³), integrating Hex and Hex-root operations in parallel to enhance efficiency. The proposed design achieves a new benchmark in performance over existing designs. Experimental findings validate the scalability and performance of the proposed architecture, establishing it as a reliable choice for ECC-based cryptographic solutions.

Offset broadside coupled lines are widely used in directional couplers and quadrature hybrids. Ideally, these lines can achieve good isolation characteristics, but in the case of multi-section lines, the characteristics deteriorate due to the effect of junction discontinuities between lines. We propose a novel equivalent circuit model of junction discontinuities and a method for extracting equivalent circuit constants to understand this effect and design a compensating structure accurately. Using this proposed method, we modeled a multi-section quadrature hybrid coupler. We constructed a circuit model of the multi-section quadrature hybrid that agrees well with the results of full-wave electromagnetic(EM) simulations. This method enables simple and efficient structural design of complex circuit structures with multi-section coupled lines that require several hours or more for EM simulation.

This study applies a topology optimization approach to the design of a Junction Termination Extension (JTE), which is one of the edge-termination structures for vertical GaN power devices. Conventional parameter optimization requires independent tuning of the width, depth, and impurity concentration of the JTE region to achieve the desired breakdown voltage. As the number of target regions increases, the combinations of design parameters grow explosively. Consequently, severe constraints such as enforcing identical impurity concentrations across regions are often imposed, which substantially limit the design freedom. Focusing on the fact that a JTE structure can be represented as a dose distribution, we perform optimization with high design freedom using topology optimization. Since breakdown voltage correlates with the maximum electric field strength under reverse bias, we optimize the dose distribution to reduce the maximum electric field strength of the device. For a vertical GaN device biased at 900V in reverse, the proposed method reduces the maximum electric field strength by 12.5% compared with a structure obtained by parameter optimization.

This paper presents a high-resolution second-order delta-sigma (ΔΣ) ADC in 22nm FD-SOI technology. To overcome the trade-off between voltage headroom and linearity, a buffered dynamic body-Biased (BDBB) gate-bootstrapped switch is introduced. This structure decouples the input signal from the parasitic body capacitance, effectively suppressing harmonic distortion and minimizing aperture jitter. The modulator employs a cascaded integrator feed-forward (CIFF) architecture with gain-boosted op-amps, achieving a peak signal-to-noise and distortion ratio (SNDR) of 104.9 dB and an effective number of bits (ENOB) of 17.1 bits in a 10kHz bandwidth. A digital decimation filter performs 640× downsampling to provide a 24-bit output. Operating at a 1.2 V supply and 12.8 MS/s sampling rate, the proposed design achieves an spurious-free dynamic range (SFDR) of over 100 dB, making it highly suitable for high-precision signal acquisition.

In this letter, a 38 GHz asymmetric Doherty power amplifier (PA) that utilizes common-source (CS) amplifiers with different gate widths for the main and auxiliary PAs to align their optimal load impedances. Both the input quadrature hybrid network (QHN), output power combiner and inter stage matching network are designed by transformer-based structure. Furthermore, a quarter-wavelength impedance inverter is integrated into the output power combiner using a π-type C-L-C network, resulting in a more compact topology. The proposed Doherty PA, implemented in 65-nm CMOS process with a compact core area of 0.6×0.42 mm². At 38 GHz, the measured saturated output power (P_sat), 1-dB output compression point (OP1dB) and peak power added efficiency (PAE) are 19.7 dBm, 19.2 dBm and 25.4 %, respectively. The measured PAE at 6-dB power back-off (PBO) is 19.1 %.

In Systems-on-Chips (SoCs), logic locking is a vital technique for protecting Intellectual Property (IP) cores from leakage. Existing logic locking schemes based on Homomorphic Encryption (HE) employ a serial-blocking architecture, embedding high-latency cryptographic modules into the processor’s data path. This approach incurs significant performance overhead and limits the achievable security level. To address this bottleneck, this paper presents Homomorphic Feedback Locking (HFL), an architecture that decouples HE operations from the CPU’s execution path into a parallel, non-blocking feedback loop accessed via Control and Status Registers. We implemented HFL in a RISC-V SoC, characterized the privilege escalation event intervals under a system call workload, and developed a queuing model to analyze its performance overhead. Experimental results show that HFL with 83-bit security incurs a System Call performance overhead of only 15.0%, an improvement over the 33.5% overhead of a 41-bit serial-blocking scheme. Our model predicts performance scaling, explaining the overhead as a function of cryptographic workload and event arrival rate.

In this letter, a 0.2-20 GHz ultra-wideband low-noise amplifier is proposed and fabricated using a 0.15-μm E-mode GaAs pHEMT process. To achieve high performance across ultra-wide bandwidths, we innovatively propose a design methodology that systematically integrates parasitic parameters as core design variables. Based on the methodology, a negative feedback topology along with an ultra-wideband decoupling network is designed and have been implemented. The fabricated chip exhibits a gain of 15.6 dB across the 0.2-20 GHz range with a gain ripple of ±0.6 dB and a noise figure below 1.86 dB. S₁₁ and S₂₂ are better than -12 dB and -8 dB, respectively. The proposed LNA also achieves an OP_1dB of 17 dBm and an IP_1dB of 1.4 dBm under a power consumption of 400 mW. Additionally, the fabricated LNA occupies a chip area of only 1.5 × 1.0 mm², including all pads.

This paper proposes a bandgap reference (BGR) voltage source with high power supply rejection ratio (PSRR), low temperature coefficient (TC), and high robustness for automotive chip electronic systems. To reduce the temperature coefficient and save chip area, a self-biased high-order temperature compensation technology is developed in the design. The proposed BGR is implemented based on 180 nm process, with an effective area of only 0.01 mm². Experimental results show that under a supply voltage of 3.3 V, it outputs a reference voltage of 1.2 V, with an average temperature coefficient as low as 2.2 ppm/℃, a PSRR of up to −120 dB at the DC operating point, and a process coefficient of variation (σ/μ) of only 0.06%, which can meet the application requirements of automotive chips for high - precision reference sources.

Compared with single-edge designs, dual-edge-triggered flip-flops (DETFFs) can maintain the same data throughput while operating at half the clock frequency. However, when integrating ferroelectric nonvolatile structures with selector-based DETFFs, the uncertain logic levels of the clock and data signals during the restore phase may lead to unintended ferroelectric field-effect transistor(FeFET) programming. In addition, conventional C-element-based flip-flops suffer from limited performance. To address these issues, this paper presents an input C-element design that enforces input isolation by generating complementary outputs during the restore process, along with an improved output C-element. Experimental results show that, compared with existing C-element-based flip-flops, The proposed design reduces operating power by at least 33.3%, and decreases hold time by at least 58.8%. In addition, the clock-to-Q delay is reduced by at least 9.2%. The proposed flip-flop is capable of storing its output state prior to power-off and effectively isolating both data and clock signals during restoration, enabling accurate recovery of the pre-shutdown state while improving C-element performance.

This brief presents an ultra-low voltage (ULV) charge pump (CP) topology with high power conversion efficiency (PCE) designed for ultra-low supply voltage, low-power on-chip applications. The proposed ULV-CP employs a combination of dynamic gate-bias (DGB) and forward body-bias (FBB) techniques with the objective of enhancing overdrive voltage and reducing conduction losses, thereby enabling operation at ultra-low voltage. A 4-stage ULV-CP has been designed and implemented in a 22-nm FD-SOI process. Measurement result shows that it can reach a peak PCE of 83.87% at a supply voltage of 0.36 V. Compared to other CP circuits, the proposed circuit outperforms in terms of PCE, maximum output power, and minimum supply voltage.

In this letter, an optimal switching pattern-based asymmetric three-phase decoupled modulation strategy for six-phase inverter-fed dual three-phase PMSM drive is proposed to improve the steady-state performance, as well as maintain a low switching frequency. Therein, the equivalent voltage vectors for the decoupled voltage vectors in harmonic plane are established. An optimal switching pattern for asymmetric three-phase modulation strategy considering current harmonic suppression is proposed. Comparative studies are conducted to demonstrate the effectiveness of the proposed modulation strategy.

Data-retention flip-flop (DRFF) efficiently maintains data during sleep mode and retains state during transitions between active and sleep mode. This paper proposes a novel source-biased stacked inverter (SBS-Inverter) and a low-leakage, structure-reused DRFF. The sleep latch circuit constructed using the SBS-Inverter can effectively reduce the power of DRFF when storing data. Reuse of the structure improves the situation of redundant transistors in certain DRFF. Fine-grained inverter level optimization reduces delay and power during the active mode. The DRFF was implemented using a 55 nm process and subjected to comprehensive analysis. Post-layout simulation results at a supply voltage of 0.4 V indicate that the proposed DRFF’s data retention leakage power is only 5.3 pW. At a supply voltage of 0.8 V, the power-delay product is only 0.146 nW*ns@20 MHz. Monte Carlo simulation results considering process, voltage and temperature (PVT) variations show that the proposed DRFF can operate reliably down to a supply voltage of 0.4 V.

Power consumption is a critical challenge in integrated circuit (IC) design. Since post-synthesis power simulation is time-consuming, fast and accurate pre-synthesis power estimation, especially at the register-transfer level (RTL) stage, is essential for guiding power optimization. However, existing RTL-stage power models struggle to simultaneously achieve cross-design generality and time-based resolution, and often rely on large-scale labeled training datasets. We present AtomPower, a general machine-learning (ML)-based power modeling framework for per-cycle power estimation across diverse RTL designs. AtomPower introduces the register structure tree (RST) to decompose a circuit into a fine-grained, bit-level structural representation, enabling accurate time-based power modeling. To address multicollinearity in regression and derive reliable power labels, we develop a finite greedy clustering (FGC) algorithm that specializes conventional clustering methods by incorporating structural constraints. In addition, we propose a tailored data augmentation strategy to significantly reduce the reliance on large labeled datasets during training. Evaluated on a diverse set of designs, AtomPower achieves a Mean Absolute Percentage Error (MAPE) of 5.02% and a correlation coefficient (R) of 0.85, outperforming state-of-the-art RTL-stage power models in both estimation accuracy and data efficiency.

This paper proposes an external frequency synchronization control circuit for DC-DC converters, in which the frequency synchronization pin (SYNC) is shared with the enable pin (EN),enhancing chip compactness and reducing cost. The chip's enable state is not affected by the external clock signal. An internal phase-locked loop (PLL) ensures the continuity of the switching frequency variation, thereby avoiding output voltage overshoot caused by abrupt frequency changes. The chip supports a frequency synchronization ranging from 200 kHz to 2.4 MHz and is implemented using SK hynix's 0.18 μm BCD process. Test results show that the maximum output voltage overshoot is 58 mV with a 1 A load current and 1 MHz synchronization.

This work presents HiTAN, a hierarchical reverse modeling framework for automated analog IC sizing. Unlike conventional forward modeling, HiTAN directly infers design parameters from target performance specifications through an automated simulation-preprocessing pipeline combined with a lightweight multi-task attention mechanism. Validation on two representative LDO topologies demonstrates that HiTAN achieves high prediction accuracy, with an average parameter error below 2% and overall performance prediction accuracy exceeding 97%. Compared with baseline models, HiTAN consistently reduces design errors by a significant margin and generates parameter sets that satisfy multi-dimensional performance constraints, thereby enhancing circuit stability, efficiency, and robustness. These results confirm that reverse modeling not only accelerates the analog design process by reducing simulation overhead but also improves design quality and scalability for complex analog IC tasks.

In non-laboratory settings, high-precision detection of methane gas is vulnerable to noise and environmental interference. To address this issue, we propose a methane detection system that utilizes tunable semiconductor laser absorption spectroscopy technology combined with second harmonic detection. This system employs a hardware-algorithm collaborative design architecture to effectively suppress noise. In comparison to commercial non-dispersive infrared sensors, the detection limit of our system is reduced to 4.81 ppm, demonstrating enhanced long-term stability. The Allan variance is measured at 4.38×10^-7 over a duration of 147 seconds. Experimental results indicate that the system exhibits good response linearity within the range of 0-1000 ppm, with a coefficient of determination (R²) of 0.9818. This research offers a reliable solution for industrial methane monitoring, and the portable design concept may serve as a valuable reference for the development of other gas sensing systems.

A compact fundamental 140 GHz mixer using our in-house 80 nm T-gate InP HEMT process is designed, fabricated and characterized. A compact resistive topology is designed to enable low power consumption, high conversion gain and high integration. Measurement results show a maximum conversion gain of -9 dB and an IF bandwidth of 15 GHz within the 130 GHz-150 GHz range under a LO power of -1 dBm. The proposed resistive mixer features a compact size of 0.63 mm × 0.9 mm and can be fabricated with InP HEMT LNA on the same wafer. The results demonstrate that the mixer is well suited for integrated terahertz receiver front-ends.

This paper presents an 8-bit, 2-GS/s, time-interleaved analog-to-digital converter (TI-ADC) for communication systems. Featuring self-calibrating dynamic comparators in the sub-SAR ADCs to minimize offset and improve overall linearity. It breaks through the limitation that the offset calibration of traditional comparators tends to introduce quiescent power consumption. A circuit and layout for the TI-ADC have been designed in 40nm CMOS. Operating at a 1-V supply voltage and 2-GHz clock frequency with a Nyquist frequency input, the design achieves a SNDR improvement from 42.11dB to 47.11dB, and a SFDR improvement from 60.46dB to 63.64dB. The power consumption is 25.79mW.

The interconnection harness undertakes the critical task of power and signal transmission between in-vehicle electronic devices, and its electromagnetic compatibility (EMC) constrains the safety of vehicle systems. As the number of in-vehicle electronic devices increases and wiring becomes increasingly complex, the electromagnetic interference (EMI) issue between cables has become more prominent. Multiconductor transmission line (MTL) models suffer from limited computational efficiency when applied to the electromagnetic analysis of complex automotive wire harnesses. Although the equivalent cable bundle method (ECBM) offers an effective means of model reduction, it is commonly developed under the assumption of an ideal infinite conducting ground plane, which restricts its applicability in realistic vehicular environments characterized by finite metallic boundaries. To overcome this limitation, this paper presents an enhanced electromagnetic modeling approach within the ECBM framework, in which the effects of orthogonal finite metallic boundaries are explicitly incorporated into the per-unit-length parameter extraction. The proposed method is therefore well suited for automotive electromagnetic environments dominated by a limited number of nearby metallic structures. Simulation results demonstrate that compared with the MTL model, the proposed method can accurately predict crosstalk responses and radiation characteristics, with the simulation efficiency improved by approximately 50%. This method provides a new solution for vehicle EMC design and analysis.

The efficient physical memory allocation is essential for high performance, particularly in architectures that support translation look-aside buffer (TLB) coalescing. The binary buddy system (BBS) is a widely used page allocator that operates in the block level. However, it enforces rigid power-of-2 block size constraints. This constraint undesirably incurs memory fragmentation and can degrade the memory system performance. To resolve this issue, we propose an architecture-specific allocator, namely a page-table level aware buddy system (LBS). Considering modern embedded system on a chip (SoC), where input/output (I/O) devices run high-bandwidth 2D data applications, we present the algorithm, an analysis, and performance experiments. The experiments indicate that, by integrating TLB coalescing, LBS can significantly reduce fragmentation and improve memory system performance.

Photoacoustic imaging is a hybrid imaging modality that combines optical and ultrasound imaging, achieving the high contrast of optical imaging together with the high resolution of ultrasound imaging. Although commercial preclinical devices for photoacoustic imaging are available, they often suffer from a limited angle of view. In this paper, we present a three-dimensional (3D) photoacoustic imaging system employing a hemispherical ultrasound probe to overcome this limitation. Using the proposed system, we demonstrate the visualization of carotid thrombosis in a mouse model.

This paper presents a multi-step interpolation structure Time-to-Digital Converter (TDC) with a wide dynamic range, high resolution, and a robust anti-PVT mechanism. The architecture is based on a coarse counter, a middle-step interpolator implemented by a PLL, and a fine-step interpolator consisting of a multi-quadrant 2-D Vernier array. The coarse counter extends the TDC's measurement range, while the middle-step interpolator, as a key component of the PVT calibration module, significantly reduces nonlinearities caused by process, voltage, and temperature (PVT) variations. The proposed multi-quadrant 2-D Vernier array doubles the measurement range of the fine-step interpolator, while maintaining the TDC's resolution. The TDC was implemented in 180nm standard CMOS technology, with a reference clock frequency of just 10MHz, achieving a detection range exceeding 25µs and a fine resolution of 5.36 ps. To further compare the nonlinearities of the proposed multi-quadrant 2-D Vernier array with the traditional 2-D Vernier wide range comparator array, an existing theoretical model is used to analyze the DNL and INL, and both of them exhibit significant advantages and an optimization of over 50% can be theoretically achieved.

The wireless power transfer (WPT) system is widely used for its convenience. However, how to address the problem of misalignment is a hard problem to solve. This paper proposes a design method for an output-parallel Series-Series (SS) WPT system based on a designed splitting coil coupler. The method aims to optimize the parameters of coil structure based on the multi-island genetic algorithm. Besides, by designing splitting coils and specific parameters, the performance of misalignment tolerance of multi-channel coils is improved, and the detailed analysis is proposed as well. Finally, A 3.3kW splitting coil WPT system prototype is built. Compared to the traditional design, the proposed design can achieve a higher coupling with the same misalignment distance, as well as less power loss by the designed splitting coils.

High-speed Field-Programmable Gate Array (FPGA) packet-processing typically relies on streaming buses such as AXI-Stream for their explicit packet semantics, but high-speed I/O blocks including 200-400 Gbps Ethernet MACs and PCIe IP cores expose segmented buses that deliver multiple fixed-width segments per cycle. This mismatch motivates the need for efficient streaming-segmented bus conversion. This letter presents a structured FPGA architecture for bidirectional conversion between streaming and segmented buses, and demonstrates a prototype on AXIS and Intel Segmented Client Interface. The design integrates a high-speed dual-buffer organization with a metadata-driven mechanism that extracts frame-boundary and sideband information early in the pipeline. By decoupling control signals from payload, the proposed architecture shortens the critical path of the extraction Finite State Machine (FSM), thereby achieving high-frequency performance. The prototype implementation on an Intel Agilex 7 FPGA achieves 400 Gbps throughput at 415 MHz on a 1024-bit bus for packets of 128 bytes and above, with less than 3% resource usage. The architecture is parameterizable and can be mapped to other streaming and segmented bus formats with minor interface adaptation.

This paper proposes a disturbance-observer-based tuning-free controller (TFC) for magnetic-geared motors (MGM). To address the difficulty of conventional active damping controllers (ADC) in suppressing the flexible elements of magnetic gears and load inertia disturbances in MGM applications, a disturbance observer is introduced to enhance robustness. A detailed parameter design procedure is provided in the discrete domain, and theoretical analysis compares the suppression performance of the conventional ADC and the proposed TFC. Finally, experiments on the MGM prototype platform demonstrate that the proposed TFC exhibits stronger robustness against load inertia disturbances.

This letter presents a novel five-order Ka-band bandpass filter based on micro electromechanical system (MEMS) technology. The basic structure using air-filled with internal coupled lines and fully enclosed metal cavity has advantages of low dielectric and radiation loss, compact size, which is conductive to the design of high-frequency passive components. The resonant unit consists of metal cavity and parallel arranged open and short-circuited metal cores. Detailed design method is given to guide the Ka-band filter design. Moreover, it demonstrates the successful application of classical microstrip filter synthesis theory to the design of a complex 3D cavity-based MEMS filter. To enable easy integration with RF systems, a standard 50-Ω interface with ground-signal-ground (GSG) transition is added to the designed filter. Finally, the filter is fabricated and measured, and good agreements between the simulated and measured results are achieved.

This letter introduces a design methodology for a broadband high-efficiency power amplifier (PA) that incorporates a new symmetrical triangular low-pass filter with Embedded Radial Stub. To extend the design space, a resistive-reactive series of continuous inverse modes (Res.-Rea. SCIMs) theory is employed. The proposed filter, which serves as the output matching network of the PA, is constructed with dual-triangular symmetric (DTS) microstrip lines and a radial stub, which are interconnected by microstrip lines. By combining a DTS filter and a radial stub, a new filter with improved performance has been proposed. The new filter achieves low passband loss, high out-of-band rejection, and narrow transition bandwidth. These characteristics are well utilized in the inverse Class-F power amplifier, resulting in excellent performance. It is applied to the output matching circuit to realize a broadband high-efficiency PA. To validate the effectiveness of the proposed structure, a PA prototype is designed and fabricated with a 10-W GaN HEMT device. Measurement results demonstrate a bandwidth from 0.6 GHz to 1.4 GHz, with a drain efficiency (DE) of 66.3%-73.3%, a gain of 9.53-12.17 dB, and an output power of 39.53-42. 17 dBm.

A vector-processor architecture based on the RISC-V extended instruction set is proposed and evaluated for the acceleration of post-quantum cryptographic(PQC) algorithms. The core employs an in-order, partially four-way multi-issue pipeline and delivers a significant speed-up over pure-software RISC-V implementations. Unlike previous hardware–software co-designs that target specific PQC schemes, the instruction-set extensions are derived from fine-grained, fixed-point arithmetic primitives; consequently, the same core can speed up current NIST candidates and tolerate future algorithm updates while remaining useful for other cryptographic workloads. The processor was implemented in 28nm SMIC HKE+ process, and post-layout simulations were conducted. Results showed that under primary PQC standards, compared with the state-of-the-art counterparts, it can achieve a reduction in total cycles by 9.1%-12.7%. In terms of stream cipher, block cipher, and hash cipher algorithms, it can achieve 12×-24× performance improvement, which enables it to have higher flexibility in practical application scenarios.