A method for designing a broadband high-efficiency power amplifier (PA) based on a novel loop-shaped filter matching structure is proposed in this paper. By combining a power amplifier matching circuit and a loop-shaped filter structure, a broadband high-efficiency PA based on a new harmonic matching structure is realized. The novel loop-shaped filter can control the second and third harmonics in a wide frequency range and has a specific control effect on higher-order harmonics, which can further expand the bandwidth of class-F PA and improve efficiency. To verify its feasibility, a power amplifier with a bandwidth of 1.6 GHz-3.4 GHz, a saturated output power greater than 41 dBm, a drain efficiency of 65% -72% with a gain greater than 10dB is designed and fabricated using GaN HEMT CGH40010F transistor.

This paper presents a fully integrated Ku-band transmitter front-end with high image rejection ratio (IRR), local oscillator feedthrough (LOFT) suppression, gain and output power for point-to-point (P2P) communication. To avoid the bulky off-chip image-rejection filter, the Hartley transmitter structure is employed, in which frequency plan is undertaken to improve the IRR and LOFT performance, and a two-stage polyphase filter (PPF) and an in/quadrature-phase (I/Q) Gilbert mixer are utilized to improve the IRR further. With the capacitive neutralization and transformer-based series power combining techniques, a two-stage power amplifier (PA) is used to obtain high gain and output power. In the LO buffer, a flexible phase inverting cascode structure is used to achieve reliable up-sideband operation, and the inductive peaking technique and cross-coupled transistor pair are employed to promote the LO swing. Fabricated in a 65-nm CMOS process, the proposed Ku-band transmitter occupies a chip area of 0.98 mm², and consumes 304-mW power consumption from a 1.2-V supply voltage. With measurements, over 15.8-17.9-GHz radio frequency (RF) bandwidth, the transmitter achieves an IRR and LOFT suppression ratio of 45-55 and 43-52 dBc, respectively. Moreover, it exhibits a conversion gain of 28.5 dB, an output 1-dB compression point (OP_1dB) of 13.3 dBm and a saturated output power (P_sat) of 16 dBm.

A novel compact 4-way ultra-wideband short pulse power divider (PD) based on coaxial waveguide is proposed in this paper. A nylon conical shell is inserted to replace the original transformer oil with an air block at the resonant place of PD to widen the working bandwidth. The junction of all inner conductors is smoothed to increase the fidelity and power capacity. The proposed PD is fabricated and tested. The results show that return loss is better than 12 dB from 191 MHz to 1.33 GHz. The amplitude loss is less than 10% and fidelity is more than 0.95 when input by impulse with full width at half maximum (FWHM) of 1.24 ns.

Since the single-sided linear induction motor not only produces thrust, but also produces vertical and transversal forces, if no specific control is applied, vertical and transversal forces can have a negative effect on the load propelled by the motor, especially in the application of the railway transit. Therefore, the best solution to the above issues is to independently control the vertical force or transversal force without changing the thrust in the motor. First, this paper presents a 3-D electromagnetic forces, i.e. thrust, vertical and transversal forces, decoupling strategy for the single-sided linear induction motor based on a novel equivalent circuit considering the longitudinal end effect and 3-D electromagnetic forces. Then, the slip-frequency calculator, thrust observer and thrust controller in the conventional vector control for induction motors are reconstructed, and a force decoupling controller is proposed. Finally, the simulation to verify the vector control with the force decoupling controller for the linear motor is performed by using a prototype motor which is used for railway transit.

In this letter, a new miniaturized dual-band frequency selective surface (FSS) with second-order frequency responses at each band is presented. The proposed structure is designed by cascading three metallic layers that are separated by two thin dielectric substrates. The proposed FSS composed of resonant and non-resonant elements implements two independently controllable pass-bands performance. An equivalent circuit model of the structure is provided to demonstrate the filtering mechanism. The proposed FSS provides stable filtering characteristics and sharp roll-off characteristics centered at X- and Ku-band, respectively. In addition, the proposed FSS exhibits highly stable frequency responses for EM waves of different polarizations and incident angles. A prototype of the FSS was fabricated and measured, the measured results have a good agreement with the simulated ones, which verifies the excellent performance of the proposed new dual-band FSS.

This letter proposes a broadband piezoelectric energy harvesting (PEH) system based on sensorless direct resonance tuning(SDRT) technique. The PEH system consists of a frequency-tunable harvester, an energy harvesting (EH) subsystem and a control subsystem. The EH subsystem can transfer energy from the harvester to the storage. The control subsystem can detect the ambient vibration frequency and adjust the inherent frequency of the harvester using a servo motor to match the ambient vibration. Furthermore, the vibration frequency detection is based on the harvester itself rather than an additional sensor. Finally, the experimental results show that the prototyped PEH system can adjust its inherent frequency to achieve resonance in the range of 36-50 Hz. In addition, the EH performance achieved by the proposed SDRT technique can reach at least 77.6% of the manual frequency tuning method.

In this paper, a radiation-hardened by polar design 14T (RHPD-14T) SRAM cell for space applications is proposed. Performance of the proposed RHPD-14T cell is analyzed by estimating various design metrices with 65-nm complementary metal-oxide-semiconductor (CMOS) technology. The proposed RHPD-14T can tolerate all single-node upset and partial double-node upset based on combining radiation hardened by polar design technology together with reasonable layout topology. Simulation results show that write access time of RHPD-14T is 1.83×/1.59×/1.56×/1.12×/1.05× shorter than RSP-14T/QUCCE-10T/DICE/S4P8N/We-Quatro(@VDD=1.2V). Word line write trip voltage of RHPD-14T is 2.67×/2.22×/1.35×/1.29×/1.26× higher than QUCCE-10T/DICE/We-Quatro/S4P8N/RSP-14T (@VDD=1.2V). Hold static noise margin of RHPD-14T is 14.85×/7.15×/1.05× higher than DICE/S4P8N/RHPD-12T (@VDD=1.2 V). In addition, Monte Carlo (MC) simulations have proved that RHPD-14T has low fluctuation, strong stability, stable recovery ability and strong single effect upset (SEU) hardened.

In this study, a mechanical movable device is used to achieve a mechanical tuning phase shifter with adjustable substrate, which has a huge potentiality of tuning range. The main body of phase shifter is microstrip structure. The substrate has two layers with one movable layer. By moving the movable layer, the equivalent relative permittivity of component is changed and tunability is realized. The phase is -128.2° to 96.1° at 6GHz while the transmission coefficient S₂₁ is from -2.09dB to -2.70dB throughout the entire tuning process. The movable layer is better to be with high relative permittivity and relative permeability to reach a wider tuning range.

Unidirectionally coupled phase oscillators in a ring are simple structures but unsuitable for application in central pattern generators (CPGs) for six-legged walking due to coexisting stable synchronization patterns. This paper shows that the coupled oscillators can be applied to a CPG by utilizing a non-periodic signal generator as a clock. The non-periodic clock-driven coupled oscillators are implemented by a sequential logic circuit using a field programmable gate array (FPGA) and a nonlinear analog circuit. A laboratory experiment confirms that a hexapod robot mounting the implemented circuits can realize six-legged walking.

This paper presents a new topology of asymmetric half bridge which can be called capacitor improved-asymmetric half bridge(CI-AHB) by adding a DC blocking capacitor adjacent to the leakage inductance for 135W type-c power delivery applications. Its detailed operation principle is shown and explained briefly. The clamping capacitor for CI-AHB stores energy when the main switch is on. Furthermore, the main switch stress for CI-AHB is low, which allows higher transformer ratio with lower voltage-stress synchronous rectifier (SR) FET. The efficiency of CI-AHB under different conditions is shown theoretically. These features help CI-AHB topology have better efficiency for over 100W level adaptor applications with power factor correction (PFC) function of constant dc bus voltage 380V input. Finally, a 135W commercial-level prototypes, PFC with CI-AHB (95.9%) was made (16.34w/inch3 with case) with both EMI and thermal pass. A state-of-the-art summary is finally given on efficiency and density of 135W power delivery (PD) adaptors.

Radar plays a crucial role in the detection of ships, structures, drones, etc. For offshore vessels, radar is installed on the top of the ships to observe their position and the land for contact accidents and defense applications such as the Aegis system. However, the accuracy of radar position detection is limited by the uncertainty of the radar calibration. In this study, we demonstrate the determination of the position of an island with high accuracy using laser-based light detection and ranging by measuring the distance and using it as a reference distance.

This paper presents a configurable analog front-end (AFE) for low-power neural recording systems that is capable of the current-to-voltage converter, programmable gain, ultra-high input impedance, low-noise, and wide bandwidth. A 6-channel AFE consisting of 6 1-channel AFEs is also introduced in this paper. The proposed AFE is designed on a 180nm CMOS process for low noise and operates over a wide frequency range of 0.5 Hz to 2.3 kHz with low input-referred noise of 1.8 μVrms and the maximal CMRR value of 180 dB. The power consumption is 8.5 μW per channel.

This study presents the enhanced sensitivity and low temperature drift effect on the performance of a novel double-cavity capacitive pressure sensor for micr-pressure detection. For theoretical analysis, the relative capacitance change of the sensor are formulated by using COMSOL Multiphysics. In experiments, a sensor model is fabricated by 3D printing technology. The obtained result of the sensor having a flexible diaphragm shows the sensitivity is improved by employing additional double-cavity at room temperature. In addition, the temperature drift effect of the designed pressure sensor is measured and examined through comparison with the traditional sensor. The temperature drift effect can be effectively suppressed by adopting the novel structure. It is expected to realize the micro-pressure detection technology which integrates the characteristics of high sensitivity, large linearity range and low temperature drift.

This paper proposes a novel damping method for the resonance problem of the LCL output filter in the active power filter (SAPF). The wide control bandwidth of the SAPF has made this problem critical. The proposed method is based on an active damping circuit, which does not affect SAPF control. It involves an auxiliary converter connected in series with a filter capacitor to detect and inject back the resonant current as the reference signal of the converter. The stability of the proposed method is analyzed using frequency response and compared to the traditional method to prove theoretical feasibility. The experimental results demonstrate the effectiveness of the proposed method, which has a better switching harmonic suppression effect compared to the traditional method.

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( f_T). Broadband operation is achieved using an enhanced degenerated Darlington f_T-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional f_T-doubler structures, the enhanced cascode Darlington f_T-doubler structure reduces the “V_CE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher V_CE for amplifying transistors, which represents higher f_T,_peak performance. Benefiting from the proposed Darlington f_T-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181- f_T bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

The globalization of the integrated circuit (IC) industry has raised concerns about hardware Trojans (HT), and there is an urgent need for efficient HT-detection methods of gate-level netlists. In this work, we propose an approach to detect Trojan-nodes at the gate level, based on graph learning. The proposed method does not require any golden model and can be easily integrated into the integrated circuits design flow. In addition, we further design a unioned GNN network to combine information from the input side, output side, and neighbor side of the directed graph to generate representative node embeddings. The experimental results show that it could achieve 93.4% in recall, 91.4% in F-measure, and 90.7% in precision on average across different designs, which outperforms the state-of-the-art HT detection methods.

To detect a wide range of objects with one camera at once, real-time object detection in high-definition video is required in video artificial intelligence (AI) applications for edge/terminal, such as beyond-visual-line-of-sight (BVLOS) drone flight. Although various AI inference schemes for object detection (e.g., you-only-look-once (YOLO)) have been proposed, they typically have limitations on the input image size and thus need to shrink the input high-definition image down to the limit. This makes small objects collapsed and undetectable. This paper presents our proposal technology for solving this problem and its effective implementation, where multiple object detectors cooperate to detect small and large objects in high-definition video such as full HD and 4K.

This paper presents a capacitively coupled digital isolator with low power consumption and superior Common Mode Transient Immunity (CMTI). It proposes a multiple-pulse-coding architecture and a receiver with an adaptive architecture, which improve the transmission accuracy, eliminate the CMT and achieve low power consumption. The multiple-pulse-coding characterizes edge signal with multi-pulses. The receiver consists of an adaptive pre-amplifier and an adaptive comparator. Fabricated in a 0.18 μm CMOS process, the chip achieves 200 kV/μs CMTI, 60 μA static current, 250 μA dynamic current and 14 kV isolation breakdown voltage with the area of the isolation capacitance of 2×10⁴ μm².

High-bandwidth interconnects between chiplets employ parallel interfaces, whose performance is limited by inter-channel crosstalk. In order to reduce the delay uncertainty (jitter) induced by crosstalk, this work analyzes the effect of signal skew and proposes a static skew scheme and a novel dynamic skew scheme. A fast algorithm is also suggested to determine the optimal skew value for the dynamic scheme. The experiment results show that the static scheme can significantly reduce jitter for low-speed buses but fails at high speed. By contrast, the dynamic scheme reduces jitter by about 44% for low-speed buses, reduces the jitter increment due to intersymbol interference by about 71%, and is effective at a higher bus rate. The proposed signal skew schemes require no additional routing overhead.

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

In this paper, we propose a novel modeling attack approach to predict the responses of XOR arbiter physical unclonable functions (XOR APUFs), which improves the prediction accuracy and reduces the computational time. The high-dimensional mathematical model of XOR APUF is established and its weakness is analyzed. Furthermore, a modeling attack approach based on the generalized regression neural network (MA-GRNN) is introduced to approximate the responses of XOR APUFs. As a proof-of-concept, four popular machine learning algorithms are utilized to evaluate the attack efficacy of 3-XOR, 4-XOR, 5-XOR and 6-XOR APUF schemes. Experimental results show that the MA-GRNN achieves a high prediction accuracy compared to the other three modeling attack approaches while requiring less computational time simultaneously.

This article proposes a CNFET 10T SRAM cell based on Stanford Virtual Source model at 5nm technology node, through optimization design and simulation analysis to select optimum gate widths of transistors to ensure best performance in terms of stability, speed and power consumption. We compare the proposed 10T CNFET SRAM with the optimized 6T CNFET SRAM in [9]. It was found that the timing and power characteristics of the proposed 10T SRAM cell is better than that of the 6T structure, the static power consumption is greatly reduced while the RSNM is improved by 93.5%, read and write EDP are improved by 68.5% and 96%, respectively.

This letter describes the effectiveness of magnetic field intensity suppression through communication-less impedance adjustment in an inductive power transfer (IPT) system. The impedance adjustment scheme comprises a circuit configuration design that enables adaptive reactance adjustment using a field-effect transistor (FET) bridge-based variable reactor, which includes a coupling-coefficient estimation method for adjusting load resistance. The experimental results show that the load impedance that minimizes the magnetic energy stored in the IPT system can suppress the magnetic field intensity by up to 16.5% with only a 4.8% decrease in power transfer efficiency compared to load impedance that maximizes the power transfer efficiency.

This paper presents a high-linearity passive double-balanced mixer with an integrated driver amplifier using the 0.25 um GaAs pseudomorphic high electron mobility transistor (pHEMT) process. We adopt a novel diode structure, which improves the linearity of the mixer by increasing the mixer’s intermodulation rejection ratio. An improved Marchand balun is designed to reduce the chip area and simultaneously have a low amplitude and phase imbalance. As a result of the integrated driver amplifier, this mixer can achieve frequency conversion at a lower local oscillator (LO) power. The proposed mixer’s radio frequency (RF) bandwidth is 1.7-4.3 GHz, and the intermediate frequency (IF) bandwidth is DC-1.2 GHz. The experimental results demonstrate that this mixer has an input 1dB compression point (IP_1dB) range of 20-23 dBm and a third-order input intercept point (IIP3) range of 25-35 dBm at 0 dBm LO drive. This mixer’s conversion loss within the operating frequency band is 8.5-10 dB. The LO to IF isolation is over 30 dB, and the RF to IF isolation can reach 50 dB. The total chip area is 1.4x3mm².

A novel quasi-planar five-port E-plane waveguide power divider with new computer-aided design method is proposed, which lower down the fabrication costs and expand application of waveguide components in the higher frequency ranges, integrations and massive die-casting productions of microwave circuits. A sample, planar five-port E-plane power divider operating between 3.1 GHz and 3.6 GHz, is designed from an initial concept of the well-known branch-line waveguide coupler. The sample circuit is fabricated and measured. Tested results show that the input reflection is lower than -25 dB, insertion loss lower than 0.1 dB. The amplitude difference between two output ports is smaller than 0.04dB, and the phase difference between the two output ports smaller than 0.3 degree.

This paper discusses issues of sampling circuits in analog-to-digital converter (ADC) and reviews some papers describing challenges for the solution to this fundamental issue of ADC. The energy consumption of the ADC is essentially determined by the capacitance. The peak current of the input signal sampling circuit is about 10 times larger than that of the continuous-time (CT) circuit and increases with resolution and conversion frequency. A CT-pipelined ADC using an analog delay circuit has been proposed to address this issue. Noise in the sampling circuit has been considered unavoidable and large capacitance has to be required to suppress the noise, but it has been shown that noise can be suppressed by placing an amplifier in front of the sampling circuit and changing the position of the sampling timing.

The Electric Mopeds (EM) drive system has the characteristics of frequent startup, rapid change of load disturbance and difficulty of establishing accurate mathematical model, this study proposes a model-free double Fractional-Order integral sliding mode control (DFOISMC). Firstly, a new double Fractional-Order integral sliding mode surface is proposed to enhance the robustness and improve the dynamic response, and to improve flexibility of the conventional integral sliding mode controller (ISMC). Secondly, a super-twisting structure is chosen to suppress chattering phenomenon. Then, the model-free DFOISMC is constructed by utilizing the double Fractional-Order integral sliding mode surface, the super-twisting approach law and the ultra-local dynamic model of EM drive system. Furthermore, the stability of the closed-loop control system under the model-free DFOISMC is proved by the Lyapunov stability theorem. Finally, the digital simulation results demonstrate that the proposed control strategy is highly effective and superior.

This paper presents a fully passive 2nd-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) designed specifically for low-power and low-cost Internet of Things (IoT) applications. By optimizing the coefficients, a substantial 24 dB in-band quantization noise suppression is achieved. To further reduce power consumption and the total unit capacitor count, a hybrid switching procedure and optimal logic are utilized. The measurement result shows that this design achieves an effective number of 10.31 bits over a 3.125 MHz signal bandwidth. At a power supply of 1.8 V, the power consumption is measured to be 728 µW with a sampling rate of 50 MS/s. Fabricated in 180-nm CMOS technology, the ADC core occupies an area of 0.117 mm². The Schrier figure-of-merit (FoM) of 160.13 dB is obtained.

An Ultra-wideband (UWB) bandpass filter (BPF) based on an elliptical open stub-loaded resonator (EOSLR) and dumbbell-sided cross-circle (DSCC) defected ground structure (DGS) is proposed in this paper. The measured results show that the 3 dB bandwidth of the filter is 3.49 ∼ 11.04 GHz, the skirt factor (S.F) is 0.844, the upper stopband rejection is greater than 20 d B at 11.70 ∼ 26.80 GHz, and the stopband width is 15.1 GHz. The proposed filter has the advantages of high selectivity and extremely broad upper stopband and it can be applied in UWB Wireless communication system.

In this letter, a low numerical dispersion error single field (SF) hybrid implicit explicit (HIE) finite-difference time-domain (FDTD) method with artificial anisotropic (AA) parameters, AA-SF-HIE-FDTD for short, is proposed. Based on the formulas of the SF-HIE-FDTD method and by introducing the electric artificial anisotropy parameters, the updated functions for 3-D AA-SF-HIE FDTD can be obtained. The numerical dispersion relation of the AA-SF-HIE-FDTD by Fourier method is investigated. Compared with the conventional SF-HIE-FDTD method, it is found that AA parameters can improve numerical dispersion relation for SF-HIE-FDTD method.

Transcatheter renal denervation (RDN) has emerged as a novel treatment option to lower blood pressure (BP) by ablating the renal nerve. However, inconsistent results of failing to reduce BP were reported, primarily due to the inability to confirm ablation temperature at the treatment area. In order to address this, we proposed a microwave balloon catheter with a hybrid machine learning (ML) algorithm to achieve a deeper ablation and predict the temperature. Through an in silico evaluation using a human body model TARO, the proposed method achieved 1.5°C difference compared to simulation using TARO, showing the proposed ML method capability.

The balance between computational performance and power consumption is a key constraint in computing systems, with integrated circuit technology posing a bottleneck. Approximate computation can trade off accuracy for performance or power improvement in error-tolerant scenarios. Division, with high computational demands and latency, is a bottleneck for computational efficiency. We propose a quadratic interpolation approximate divider (QIAD) based on multiplicative division, which has superior statistical performance. The design is simulated and synthesized at TSMC 65nm process and tested on image color quantization, showing the best quantization effect using evaluation indicators such as PSNR, MSE, and SSIM.

Aiming at the problems of high complexity and large calculation quantity in the existing digital control strategies for single-inductor dual-output (SIDO) converter, this paper proposes a simple and reliable digital compensation control technology to suppress the cross-regulation. The design of the compensation control is only related to the selected circuit topology, thus it will not be redesigned for different control strategies. Taking the digital predictive current-mode (DPC) controlled SIDO buck converter as an example, the small signal model is firstly established. Based on these transfer functions, the theory of the proposed digital compensation method, which can suppress cross-regulation is analyzed. In the meanwhile, the digital control algorithm is derived. Simulation and experimental results verify the correctness of the theoretical analysis.

This paper presents a novel compact and broadband filtering balun using N-shaped spoof surface plasmon polaritons (SSPPs). The N-shaped SSPP unit cell’s lateral size has a 48% reduction compared to the rectangle-shaped counterpart. The proposed filtering balun is constructed by periodically etching N-shaped and mode-matching SSPP unit cells into the slotline balun consisting of the microstrip-to-slotline transition (MST) structures. The combination of the N-shaped SSPP unit cells and slotline balun realize the compactness and the broadband bandpass filtering response. Moreover, we can individually adjust the passband’s lower and upper cut-off frequencies. Due to the larger phase constant of the N-shaped SSPP unit cell, the field-confined ability of the proposed filtering balun is enhanced. The proposed design is fabricated and measured. It has advantages in bandwidth, stopband performance, size, and degree of design freedom compared with existing SSPP filtering baluns.

In-situ timing monitor is widely used in the adaptive voltage scaling (AVS) system to eliminate the excessive design margin preserved for PVT variation. However, most of them suffer from the short-path (SP) issue where SPs must be padded to exceed the speculation window, incurring significant area overhead. A new in-situ timing monitor based on timing-error prediction is proposed in this paper, which can monitor the timing of the circuit across a wide voltage range. The SP issue is resolved by an SP isolation unit, and the speculation window is carefully determined to guarantee accurate timing-error prediction. A lightweight 13-T transition detector (TD) is designed to detect timing violations of critical paths. Furthermore, the proposed method is APR-friendly to EDA tools. All the proposed techniques are implemented in a CORDIC chip for demonstration targeting the SMIC 55nm CMOS process. Results show that the whole design achieves up to 53.2% energy saving with 6.1% area overhead as compared to the typical margined baseline circuit.

For multi-input piezoelectric energy harvesting, the issue of energy backflow between multiple Piezoelectric Transducer (PTZ) cause energy loss. Hence, an Isolated Active Rectifier (IAR) is proposed in this paper to address the problem. Based on the characteristic of energy isolation, the Multi-Input Synchronous Electric Charge Extraction Circuit (MI-SECE) with IAR can harvest energy from multiple PZTs with the arbitrary phase difference. The peak overall power conversion efficiency can reach up to 85.5%.

Traditional von Neumann architecture bottlenecks such as the “memory wall” limit artificial intelligence (AI) development, and in-memory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.

Reliable power supply is of great significance to the stable operation of the online monitoring device. This paper studies a kind of electric energy collection power supply based on the principle of current mutual inductance. The iron core is made of nanocrystalline alloy with high permeability, and the relationship between the number of turns and the energy consumption power is analyzed by equivalent circuit. A discharge circuit is formed by connecting multiple diodes in series to avoid oversaturation of the iron core, and the residual voltage on the diode supplies the load electric energy. Combined with simulation and experiment, the number of turns and the number of diodes in series are optimized, so that the power supply has high efficiency and is not easy to be deeply saturated. The rectifier bridge and DC-DC voltage regulator module are used to stabilize the output voltage. The test shows that the power supply can support reliable energy extraction within the range of wire current of 17A at least and 1000A at most, and can be applied to lines of various voltage levels.

With the development of storage technology, NAND Flash’s reliability becomes more serious. The bit-flipping schemes and low-density parity-check (LDPC) codes are two effective methods to solve this problem. Motivated by error characteristics of NAND Flash and flag bits added by the bit-flipping scheme, an enhanced LLR optimization algorithm of LDPC is proposed based on the prediction of the threshold voltage state error rate (VSER) by flag bits. Compared with the conventional scheme, the proposed algorithm extends the data retention time to 25.44 times. The decoding iterations of LDPC are reduced by up to 87.74%.

This paper presents ultra-wideband 18.2-42.0 GHz LC injection-locked frequency doubler (ILFD) with transformer inputs. To expand the locking range, the proposed ILFD incorporates the transformer connected to the source of the gain-cell transistor to obtain high linearity of the input circuitry, moreover, the input matching frequency shifts from the free-run frequency of the oscillator. The measured maximum locking range exhibited 79.1% from 18.2 GHz to 42.0 GHz output at 0 dBm input power and the locked phase noise at 1MHz offset from 28 GHz carrier frequency was −112.1 dBc/Hz under 1.7 mW power consumption. Also, the lowest locked phase noise at 1 MHz offset from the carrier was −122.8 dBc/Hz under 21.2 mW power consumption, and it was only 2.2 dB degraded from the theoretical value. The process technology used in this work was TSMC-180nm CMOS.

To improve the dynamic response performance and robustness of a permanent magnet linear synchronous motor (PMLSM)-based servo system, an adaptive proportional-integral-derivative (PID) controller based on a particle swarm optimization neural network is proposed. First, according to the mechanical dynamics equation of the PMLSM, a mathematical model of the PMLSM was established. Second, an adaptive PID speed controller is designed to realize real-time control of the PMLSM. To improve the dynamic performance and stability of the controller, a particle swarm optimization neural network is used to dynamically tune the parameters. Finally, the effectiveness of the proposed controller was verified on the MATLAB/Simulink simulation platform. Compared to the traditional PID controller, the adaptive PID controller can improve the dynamic performance of the system more effectively.

Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an ‘error’ signal used to dynamically regulate the chip’s operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.

An efficient design methodology for adaptive system based on direct configuration bitstream (CB) evolution has been proposed, which models the relationship between resources and CBs of the field programmable gate array (FPGA), and then generates CBs online according to the models built. The system framework and design methodology have been given and verified on Xilinx Virtex-5 FPGA. Results show that it can implement embedded online self-programming of FPGA’s logic and routing resources via modifying CBs directly; and has lower resources overhead, lesser time consumption, and stronger adaptability than the mainstream evolution approaches.

A novel buck-boost power converter is proposed to improve the performance of switched reluctance generator (SRG) system in an electric vehicle. In the proposed topology, the energy conversion part is formed by a buck-boost circuit and additional switches, with which, it is flexible to significantly boost the magnetization voltage and demagnetization voltage, thereby the output power range is improved and the power losses are reduced. The basic structure of the proposed converter is presented first and the attached operating modes are analyzed. The control strategy of the SRG system is then made to control the output voltage and the boost capacitor voltage. The simulation results show that compared to the conventional buck-boost converter, the proposed converter enhances the efficiency and reduces the power losses.

How to replace the referee in sports with artificial intelligence has attacked a huge amount of attention recently. In this paper, non-battery pressure detection and communication system are designed and fabricated aiming to help the referee in the basketball games. To get the information from player and ball at the same time, the designed system is consisted of three parts, including the basketball monitoring system, the shoes monitoring system, and the laptop to collect and process the data. For the basketball monitoring system, eight piezoelectric polyvinylidene fluoride (PVDF) flexible thin films are used as the sensor on the surface of the basketball with the sensitivity of 0.065 V/N and four hard piezoelectric Lead Zirconium titanite (PZT) patches are set inside the ball as the power source. As for the shoes monitoring system, four PZT patches work as both power source and pressure sensor with a sensitivity of 0.025 V/N. To solve the referee problem in basketball game, time delay of different systems is first measured. The different systems have similar time delay of about 3s, which will help to make sure whether the players break the rules. In this paper, whether the player has a traveling violation in a game can be refereed by the collected data, which has more than 97% accuracy. This work shows an innovative progress in automatic referees in games and the Internet of Things (IoT) in the human health monitoring.

Approximate computing has excellent result in error-tolerant applications sacrificing computational accuracy for better performance in the area, speed, and power consumption. As the most basic operation, addition is used in a large number of applications in various occasions. Therefore it is of great importance to optimize the performance of addition computation. In this paper, a segemented carry prediction adder (SCPA) structure is proposed, which splits the long carry chain into several short chains for parallel computation. The design parameters are diversified by adjusting the size of the blocks and the prediction depth of each subadditive to achieve different levels of performance. Flexible parameter tuning allows different design goals to be achieved based on specific performance requirements, which makes SCPA a useful design guideline for approximate adders. The error performance of SCPA is mesured by MRED, NMRED, ER, and other indicators and significantly has the best statiscal performace compared to similar designs. The proposed design is synthesized under TSMC 65nm process, and the result shows that the SCPA has a very nice accuracy-power tradeoff under 8-bit and 16-bit condition.

Transient execution attack does not affect the state of processor microarchitecture, which breaks the traditional definition of correct execution. It not only brings great challenges to the industrial product security, but also opens up a new research direction for the academic community. This paper proposes a defense mechanism for SMT processors against launching transient execution attacks using shared cache. The main structure includes two parts, a security shadow label and a transient execution cache. In the face of the side channel attacks widely used by transient execution attack, our defense mechanism adds a security shadow label to the memory request from the thread with high security requirement, so that the shared cache can distinguish the cache requests from different security level threads. At the same time, based on the record of security shadow label, the transient execution cache is used to preserve the historical data, so as to realize the repair of the cache state and prevent the modification of the cache state by misspeculated path from being exploited by attackers. Finally, the cache state is successfully guaranteed to be invisible to any attacker’s cache operations. This design only needs one operation similar to the normal memory access, thus reducing the memory access pressure. Compared with the existing defense schemes, our scheme can effectively prevent Spectre attack, and the overhead of performance is only 3.9%.