IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Advance online publication
Showing 1-26 articles out of 26 articles from Advance online publication
  • Heng You, Yong Hei, Jia Yuan, Weidi Tang, Xu Bai, Shushan Qiao
    Subject Area: Integrated circuits (logic)
    Article ID: 16.20190212
    Published: 2019
    [Advance publication] Released: May 23, 2019
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    In this paper, a 16 times 16 low-power low-area asynchronous iterative multiplier is proposed. The multiplier diminishes 2 bits at a time with an iterative structure, to filter out the useless switching activities, we employ a finishing detector to dynamically detect the end of the computation and stop iteration ahead of schedule. Additionally, with the employment of finishing detectors, the proposed multiplier could provide a much faster average speed than synchronous approach. Post-layout simulation results show that the asynchronous multiplier offers up to 74% power reduction compared with the synchronous design. Simultaneously, the proposed design also exhibits a prominent area reduction compared with other non-iterative multiplier benefited from the iterative architecture.

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  • Xiaoping Zhou, Bin Wu, Kan Zheng, Zhou Wang
    Subject Area: Integrated circuits (memory, logic, analog, RF, sensor)
    Article ID: 16.20190248
    Published: 2019
    [Advance publication] Released: May 23, 2019
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    In this paper, we propose a simplified weighted least square (SWLS) to estimate phase variations utilizing pilots, for Orthogonal Frequency Division Multiplexing (OFDM) based very high throughput wireless local area networks (WLANs). For SWLS, the common phase error (CPE) maximum likelihood (ML) estimation and the angle boundary treatment are improved to enhance the performance of phase estimation, while the combined scheme of pair pilots is used to reduce the complexity. Simulation results show that, compared to weighted least square (WLS) scheme, a similar pocket error rate (PER) is achieved by using the SWLS method, but more than 40 percent of complexity is reduced.

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  • Cheng-Hung Hsieh, Yi-Ting Lin, Hsaing-Chieh Jhan, Zuo-Min Tsai
    Subject Area: Microwave and millimeter wave devices, circuits, and hardware
    Article ID: 16.20190272
    Published: 2019
    [Advance publication] Released: May 23, 2019
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    This paper proposes a new two-dimensional (2D) Butler matrix antenna array with 16 switching beams for tile-based beamforming. This study fabricated and assembled a 3.5-GHz Butler switching antenna array using multilayer Rogers printed circuit board technology. It adopted a new design concept and layer-by-layer vertical connection architecture. This 2D Butler matrix antenna array does not require long coaxial cables to connect functional circuit interfaces, which is an improvement over the traditional Butler matrix beamforming network (BFN) antenna array and may facilitate considerable reductions in circuit volume and complexity.

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  • Chunhui Fang, Wenmin Yu, Yukun Zhu, Liang Wu, Tianyu Pen, Xiaowei Sun
    Subject Area: Microwave and millimeter wave devices, circuits, and hardware
    Article ID: 16.20190187
    Published: 2019
    [Advance publication] Released: May 17, 2019
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    Signal-to-noise ratio (SNR) of the millimeter wave (MMW) three-dimensional (3D) imaging system plays a critical role in the imaging quality. The impacts of phase-locked loop (PLL) bandwidth on SNR of the imaging system is demonstrated and the relationship between SNR and imaging resolution is analyzed in this paper. Analytical and experimental results show that choosing the optimum PLL loop bandwidth can maximize the SNR and greatly improve the performance of MMW imaging system.

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  • Fang Zhou, Ning Wu, Xiaoqiang Zhang, Jinbao Zhang
    Subject Area: Integrated circuits (memory, logic, analog, RF, sensor)
    Article ID: 16.20190192
    Published: 2019
    [Advance publication] Released: May 17, 2019
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    Collision Attack (CA) has posed a huge threat to the security of AES circuit. To protect sensitive information, it’s necessary to do research on defense strategy of CA. This letter proposes a new method to defense CA through the implementation of random delay based parallel S-box. It can destroy the consistency of the power consumption curves, confuse the judgment of the collision and the setting of the collision threshold to achieve the goal of resisting the CA. Compared to the well-known random mask method and other CA countermeasures, our strategy can defense CA without changing the AES round transformation architecture and bring extra resource overhead.

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  • Jiahao Yin, Chunmeng Dou, Danian Dong, Jie Yu, Xiaoxin Xu, Qing Luo, T ...
    Subject Area: Integrated circuits (Memory)
    Article ID: 16.20190201
    Published: 2019
    [Advance publication] Released: May 17, 2019
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    There are two major challenges in developing the sensing circuit for ReRAM in deep submicron technologies, including: 1) the reduced sensing margin (SM) due to the lowered supply voltage (VDD). 2) the degraded read access pass yield caused by the increased process-voltage-temperature (PVT) variations. A Reference Clamping Sense Amplifier (RC-CSA) with Amplifier Assisted load PMOS and Dynamic Pre-charge circuit is proposed to deal with these two challenges. Simulation results show that the RC-CSA is able to provide over 200mV SM with VDD down to 0.55V, and capable to work with a large bit-line loading (4096 cells per BL). The typical read yield is 99.9% for 32-Mb macro with sensing time of 4.6ns under 0.75V VDD. Overall, RC-CSA is very suitable for low-VDD and high-density applications.

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  • Kiichi Niitsu, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
    Article ID: 16.20190218
    Published: 2019
    [Advance publication] Released: May 17, 2019
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    This study demonstrates the design and theoretical analysis of a clock jitter reduction circuit that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately four-fold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages. Theoretical analysis for evaluating the limit of jitter reduction is also presented.

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  • Fan Zhang, Yi Wang, Yang Yu, Yang Gao, Yi Zhang, Yun-xiao Peng, Cheng ...
    Subject Area: Microwave and millimeter wave devices, circuits, and hardware
    Article ID: 16.20190237
    Published: 2019
    [Advance publication] Released: May 17, 2019
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    This paper presents a compact varactor-tuned dual-band bandpass filter with independently tunable passbands and high selectivity. The filter consists of two varactor-loaded half-wavelength dual mode resonators, each of which features independent tunability of odd- and even-mode resonant frequencies by varying the capacitances of the corresponding loading varactor diodes. Benefiting from this feature, the filter offers two independently controllable passbands. In addition, hook-shape feed lines are utilized to create transmission zeros between the two passbands, which enhances the selectivity of the filter.

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  • Yicheng Zhang, Yongzhong Zhu, Zhihao Meng, Jie Zhang, Kaiwei Zuo
    Subject Area: Microwave and millimeter wave devices, circuits, and hardware
    Article ID: 16.20190255
    Published: 2019
    [Advance publication] Released: May 17, 2019
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    Based on the double folded 1/4 mode substrate integrated waveguide (DFQMSIW) resonator, a two-pole DFQMSIW tunable filter with frequency, bandwidth and transmission zeros tuning is proposed in this paper. In order to increase the stability of the filter, the constant bandwidth can be maintained by changing the coupling coefficient by two varactor diodes when tuning frequency and transmission zeros. The center frequency can be tuned in the range of 1.1GHz-1.9GHz, transmission zeros can be tuned from 1.41 GHz to 1.5 GHz with bandwidth unchanged, and bandwidth can be tuned from 120MHz to 200MHz. The insertion loss is about -1.3dB to -3dB.

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  • Zhiwei Zhang, Zhiqun Cheng, Guohua Liu
    Subject Area: Microwave and millimeter wave devices, circuits, and hardware
    Article ID: 16.20190264
    Published: 2019
    [Advance publication] Released: May 17, 2019
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    This paper proposes a broadband Class EF power amplifier based on a low-pass filter matching structure. Based on the theory of Class EF power amplifiers, the optimal fundamental load impedance required is derived. A broadband matching circuit is then designed using a low-pass filter prototype. In the meantime, a compact harmonic control circuit is proposed to meet the harmonic impedance requirements of class EF power amplifiers. In order to validate the effectiveness of the proposed method, a 2.6-3.6 GHz broadband class EF power amplifier is designed and fabricated. Measurement results show that the output power is between 40.68 dBm and 41.6 dBm at 1 dB compression point in 2.6-3.6 GHz. From 62% to 78% of drain efficiency is obtained with a gain greater than 10 dB.

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  • Hongmin Zhou, Ying Zhang, Ying Yu
    Subject Area: Integrated circuits (memory, logic, analog, RF, sensor)
    Article ID: 16.20190274
    Published: 2019
    [Advance publication] Released: May 17, 2019
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    An ultra-wideband (UWB) low-noise amplifier (LNA) exploiting noise cancelling and simultaneous input and noise matching (SINM) technique is presented. The common-gate (CG) input stage with noise cancellation topology is utilized for low-noise figure and wideband input matching. To overcome the noise deterioration induced by the noise-cancelling stages and broaden the input-matching bandwidth, simultaneous input and noise matching technique is employed. The circuit is fabricated in 180-nm CMOS technology. The measurement results show that within 3.1-10.6 GHz UWB applications, S11 is lower than -10 dB, the gain (S21) is 12.4-13.6 dB and the noise figure (NF) is 3.3-4.5 dB. It consumes 12 mA under a 1.8 V supply and occupies an area of 0.56 mm2

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  • Nam Yoon Kim, Young Bin Cho, Chang-Woo Kim
    Subject Area: Energy harvesting devices, circuits and modules
    Article ID: 16.20190220
    Published: 2019
    [Advance publication] Released: May 14, 2019
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    Beacon systems for Internet of Things (IoT) services require frequent battery replacement and costly maintenance. To resolve these issues, we developed a novel beacon system. This system does not require Power over Ethernet (PoE) to supply power because it uses Ethernet energy-harvesting technology via the RJ45 port of the router and switching hub. We experimentally confirmed that the power produced through the Internet TCP/IP network signals activated the beacon dongle to transmit signals, and that a smartphone then received these signals.

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  • Aijuan Jin, Shuo Xiang, Shaolong Li, Wenbin Cao
    Subject Area: Power devices and circuits
    Article ID: 16.20190221
    Published: 2019
    [Advance publication] Released: May 14, 2019
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    Due to the high input current harmonics created from the power diodes as well as the switching of the inverter, the power factor cannot achieve a unity power factor. This paper presents an improved active power factor correction (APFC) converter for three-phase asynchronous motor drive system. This improved APFC operating in a discontinuous inductor current mode based on bridgeless canonical switching cell is designed and corrects the power factor in grid. In order to obtain high performance of the motor drive system, the dual-mode control strategy and the fuzzy PID is used in this system. Finally, the whole system is verified by software simulation and hardware experiment.

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  • Li Zhang, Liwen Liu, Yiqi Zhuang, Hualian Tang, Beilei Xu, Junlin Bao, ...
    Subject Area: Electron devices, circuits and modules (silicon, compound semiconductor, organic and novel materials)
    Article ID: 16.20190238
    Published: 2019
    [Advance publication] Released: May 14, 2019
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    STT-MRAM has been considered to be one of the most promising non-volatile memory candidates due its non-volatility, high speed, and unlimited endurance etc. However, with technology scaling down, STT-MRAM suffers from high sensitivity to process voltage and temperature (PVT) variations. Additionally, the negative bias temperature instability (NBTI) effect has become an important factor affecting the life of the pMOSFETs used in an STT-MRAM sense amplifier. Therefore, designing a more reliable sense amplifier has become a critical challenge. In this paper, a novel architecture for a sense amplifier is proposed, which includes switching transistors to decrease the NBTI effect on the pMOS device, and a balanced transistor to decrease the sensitivity of the sense amplifier to process variations.

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  • Jie Miao, Houpeng Chen, Yu Lei, Yi Lv, Weili Liu, Zhitang Song
    Subject Area: Integrated circuits
    Article ID: 16.20190250
    Published: 2019
    [Advance publication] Released: May 14, 2019
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    This letter proposes a near-threshold single-inductor double- output (SIDO) DC-DC converter with a high-precision zero current detector (ZCD) circuit which supply voltage to phase change memory (PCRAM) chip in wireless sensor network. It has a specific startup procedure to provide wide input voltage range. And the ZCD circuit is designed according to volt-second balance theory and minimizes the duration of reverse inductor current to about 1nS. The DC-DC converter is implemented in 110nm standard CMOS process and the maximum power efficiency is 89.47% with no cross regulation.

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  • Jun Hu, Muhammad Asif, Xi Wang, ShaoJun Li, XiaoJuan Chen, Peng Ding, ...
    Subject Area: Classification: Microwave and millimeter wave devices, circuits, and hardware
    Article ID: 16.20190252
    Published: 2019
    [Advance publication] Released: May 14, 2019
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    In this letter, we present a 30 MHz-3 GHz ultra-broadband GaAs stacked power amplifier (PA) fabricated in 0.15 μm pHEMT process for many applications. The implemented PA obtains 18.9 dB ± 0.9 dB flat gain by using novel input matching networks, and better than 10 dB input and output return loss. The large-signal measurements show that the output power is 30.5 dBm ± 1.2 dB at 12 dBm input power, with a peak PAE of 30% at 400 MHz. For multi-standard system usage, the broadband PA also shows good linearity when tested with two tones and long-term evolution (LTE) signal.

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  • Ki-Chai Kim, Young-Ki Cho
    Subject Area: Microwave and millimeter-wave devices, circuits, and modules
    Article ID: 16.20190269
    Published: 2019
    [Advance publication] Released: May 14, 2019
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    This paper presents the resonance transmission of a small, square aperture with two parallel wires in a ground plane. When a plane wave excites a square aperture, aperture resonance occurs using parallel wires, which is known as resonance transmission or maximum power transmission. The resonant frequency of a 3-cm square aperture structure was reduced from 4.18 GHz to various desired frequencies by adding wires. The enhanced transmission cross sections using two parallel wires were ≈3λ2/4π (= 2Gλ2/4π, G = 1.5) for square widths of ≲0.22λ, and approached 3.56λ2/4π (= 2Gλ2/4π, G = 1.78) for square widths ≳0.22λ. The small square aperture enhanced transmission cross sections using parallel wires were between 3λ2/4π and 3.56λ2/4π.

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  • Peijin Dong, Sheng Sun, Xi Yu
    Subject Area: Microwave and millimeter wave devices, circuits, and hardware
    Article ID: 16.20190132
    Published: 2019
    [Advance publication] Released: May 13, 2019
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    In this paper, a wideband filtering antenna is designed based on the dual-frequency matching condition. Instead of matching at only one radiating frequency in the conventional filtering antenna design, an antenna element with two radiating frequencies are considered and equivalently modeled as two series-connected parallel RLC resonators, a series inductor, as well as a shunt capacitance. To obtain a wideband impedance matching, last two stages of the parallel coupled-line sections in a filter are synthesized for matching the antenna at two frequencies. Finally, a prototype of a four-pole filtering antenna is designed and fabricated. The measured results achieve a wide bandwidth of 27.8% over 2.12-2.81 GHz with a flat antenna gain of 3.41 dBi over all the filtering band.

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  • Zhengyong Yu, Jianping Zhu, Cheng Wang, Xia Yang, Wanchun Tang, Yuehua ...
    Subject Area: Microwave and millimeter wave devices, circuits, and modules
    Article ID: 16.20190178
    Published: 2019
    [Advance publication] Released: May 13, 2019
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    A new three-dimensional (3-D) frequency selective surface (FSS) based on rectangular waveguide cavities is presented, which realizes a quasi-elliptic bandpass response by multiple transmission zeros/poles. Each unit cell of the proposed FSS is composed of an empty rectangular waveguide cavity and a cuboid circuit board with two back-to-back square loops. With the help of the rectangular waveguide cavities, the electrical and magnetic coupling paths are constructed, resulting in two transmission poles. The constructed out-of-phase signal paths cause two transmission zeros in the upper stopband. To explain the operating principle of the proposed FSS, an equivalent circuit model is given and analyzed using the odd- and even-mode method. A prototype of the proposed FSS is fabricated and measured. The measured results agree well with the simulated results, and show that the FSS can achieve a stable response to variations of incident angle from 0° to 60° for both TE and TM polarizations with wide out-of-band rejection. In addition, the proposed design also realizes a relative small unit cell.

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  • Jongeun Koo, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sun ...
    Subject Area: Integrated circuits (memory, logic, analog, RF, sensor)
    Article ID: 16.20190180
    Published: 2019
    [Advance publication] Released: May 13, 2019
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    We propose a low-overhead, one-cycle timing-error detection and correction (EDAC) technique for flip-flop based pipelines. In order to prevent data collision during local clock gating for rapid error correction, the proposed technique performs clock gating of the master and the slave latches inside the flip-flops independently. Unlike previous flip-flop based one-cycle EDAC techniques, the independent clock gating in the proposed technique enables selective replacement of EDAC flip-flops, thereby reducing the area and power consumption overhead. Our experiments using a 3-stage pipeline consisting of 8-bit multipliers showed that the proposed technique improved the area and power consumption by 66% and 88%, respectively, compared to the state-of-the-art flip-flop based EDAC technique while showing a comparable area and power consumption with the two-phase latch based EDAC technique. A 32-bit, 5-stage MIPS microprocessor data path testchip based on the proposed technique was implemented in a 65nm CMOS technology. With the proposed one-cycle EDAC technique, the silicon measurement results from 31 dies showed 24.3% higher throughput and 8.7% less energy consumption beyond the point of the first failure (PoFF).

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  • Xubin Chen, Xuan Li, Yupeng Shen, Jiarui Liu, Hua Chen
    Subject Area: Integrated circuits (memory, logic, analog, RF, sensor)
    Article ID: 16.20190197
    Published: 2019
    [Advance publication] Released: May 13, 2019
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    In this paper, a 14bit 500MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40nm CMOS technology is presented. A 2.5V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. Besides, the high-voltage-thin-oxide-device design is incorporated to further improve the linearity. In the meantime, an improved supply voltage domain arrangement is proposed to achieve a single power design and improve structural power efficiency. The measured Signal-to-Noise-and-Distortion-Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 71dB and 79dBc at 120.2MHz input signal under 500MS/s. The ADC occupies an active area of 0.4mm2 and consumes a total power of 300mW.

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  • Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qia ...
    Subject Area: Integrated circuits
    Article ID: 16.20190208
    Published: 2019
    [Advance publication] Released: May 13, 2019
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    A single event upset (SEU) tolerant latch has been put forward in the current paper. By means of the parallel nodes structure design together with the layout-level optimization design, the proposed design is capable of substantially improving the immunity to SEU. In comparison with the conventional latch, the stacked latch with isolation and the dual-modular-redundancy (DMR) latch with C-element, the simulation results based on the 65nm CMOS process demonstrate that the proposed latch performs much better in SEU mitigation. For P-hit simulation, the proposed latch can achieve a correct output in the end, no matter the struck PMOS is at OFF state or ON state. For N-hit simulation, the proposed latch is also capable of mitigating the voltage transient and recovering to original state eventually.

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  • Yongqin Zhou, Lei Zhou, Bo Hu, Ran Li
    Subject Area: Power devices and circuits
    Article ID: 16.20190193
    Published: 2019
    [Advance publication] Released: April 26, 2019
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    This paper proposes a structure of permanent magnet flux-switching motors (PMFSM) using “mixed” segmental permanent magnets, which is based on analysis of the structure and the operational principle of PMFSM. The paper researches the influence of tangential and radial segmental permanent magnets on motor’s electromagnetic torque, torque ripple and cogging torque respectively, which is based on the finite element analysis of a 12/10 three phase permanent magnet flux-switching motor. The research shows that the motors using this new structure can reduce torque ripple and cogging torque by comparing with the conventional permanent magnet flux-switching motor, and the motors have negligible influence on the other performances, such as the flux linkage and the induced voltage.

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  • Tian-yu Pen, Bing Huang, Shu-Na Wang, Xiao-Wei Sun, Ling-Yun Li
    Subject Area: Microwave and millimeter wave devices, circuits, and systems
    Article ID: 16.20190231
    Published: 2019
    [Advance publication] Released: April 26, 2019
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    True time delay lines and phase shifters are widely used in RF timed/phased array systems. Conventional delay lines and phase shifters often associate with reflection type circuits or distributed (periodically loaded) transmission lines. In this paper, we propose a new type of distributed circuit which composed of uniform transmission lines built on integrated Schottky active layer. A bi-functional chip is designed based on the new distributed structure. An Archimedean spiral topology is adopted to reduce the chip area. Theoretical analysis of the design method and circuit parameters is performed and a miniaturized prototype is implemented with p-HEMT technology to validate the design theory. Measurement results shows that this chip could work as either an area-efficient true-time delay line or a low-voltage phase shifter over the bandwidth 11-15GHz. As an area-efficient true-time delay line, this chip provides 82.1ps delay time per square millimeter when the biasing voltage fixed at -1.4V. As a low-voltage phase shifter, this chip provides 26.43° phase shift per volt when the biasing voltage sweeps form 0V to -1.4V.

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  • Runyun Miao, Changchun Chai, Yuqian Liu, Hui Li, Yintang Yang
    Subject Area: Integrated circuits
    Article ID: 16.20190108
    Published: 2019
    [Advance publication] Released: April 24, 2019
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    This paper proposes a new method to improve the efficiency of boost converter under light load conditions by using the hybrid modulation of hysteresis current mode and burst mode (HCM-BM). A circuit is designed to satisfy the requirement of adaptive fast switching between HCM and BM. The whole circuit of proposed HCM-BM converter and conventional HCM converter have been built with a standard 0.18-μm CMOS process, respectively. The simulation results show that the proposed converter provides a maximum efficiency improvement of 17% under light load compared with the conventional boost converter. Meantime, it can achieve up to 74% efficiency at 10μA load.

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  • Hiroya Andoh, Keita Tsuzuki, Dai Oikawa, Toko Sugiura, Takehiko Tsukam ...
    Subject Area: Electromagnetic theory
    Article ID: 16.20190156
    Published: 2019
    [Advance publication] Released: April 24, 2019
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    In this manuscript, the simplified S-matrix of the pair of RLC circuits with resonant coupling at the resonant frequency is revealed. All of the elements of the S-matrix (S-parameters) are expressed by using essential quantities, which are the port-impedance / resistance ratios and the kQ-product. The matching condition and the maximum power transfer efficiency are analytically derived from the elements of the simplified S-matrix.

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