IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Advance online publication
Displaying 1-46 of 46 articles from this issue
  • Yuta Shiomi, Hiroyuki Torikai
    Subject Area: Integrated circuits
    Article ID: 21.20240095
    Published: 2024
    Advance online publication: March 14, 2024
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    A spiking neural network of ergodic sequential logic neuron models is presented. It is shown that the presented network is capable of reproducing various biologically plausible spatio-temporal phenomena (e.g., basic synchronization and complicated chimera phenomenon) observed in the brain. Moreover, it is revealed that the presented network is able to operate with lower power compared to a standard digital-processor-based spiking neural network. It is then discussed that the presented network will be a useful building block in a brain prosthetic device.

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  • Liu Shu, Liu Jinsong, Xu Honglu, Sun Haoyue, Wang Fuqian, Zhu Jiaxi
    Subject Area: Energy harvesting devices, circuits and modules
    Article ID: 21.20240112
    Published: 2024
    Advance online publication: March 13, 2024
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    At present, the grounding protection of flexible grounding system mostly directly adopts the zero-sequence time-limit overcurrent protection of low-resistance grounding system, which has problems such as insufficient protection sensitivity when grounding via high-resistance. The changes in zero-sequence voltage (ZSV) and zero-sequence current (ZSC) upstream and downstream of the fault point before and after the small resistor is put into operation are analyzed. The fault information collected by the synchronous phasor measurement unit (PMU) are orthogonalized. Finally, the correlation coefficient method is utilized to compare the numerical values and polarity of projection amounts between adjacent PMUs. Based on this, a fault location method based on steady-state projection is proposed in this paper. Simulation and on-site test data show that the proposed method can accurately identify the fault section under different fault conditions.

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  • Lidan Zhou, Shufang Dai, Gang Yao
    Subject Area: Power devices and circuits
    Article ID: 21.20240123
    Published: 2024
    Advance online publication: March 13, 2024
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    With the development of wind power generation, improving the accuracy of fault diagnosis in permanent magnet synchronous motor (PMSM) is crucial for reducing maintenance costs. This paper integrates signal analysis and machine learning algorithms, proposing an approach that combines the improved empirical wavelet transformation (IEWT) with the CatBoost algorithm to diagnose open-phase faults in PMSM. IEWT effectively suppresses the modal aliasing phenomenon caused by noise and spectral leakage in traditional empirical wavelet transformation, and the decomposition results can demonstrate the time-frequency characteristics of the fault signal used for training the CatBoost classification model. Experimental results indicate that the proposed algorithm achieves high overall accuracy in diagnosing open-phase faults in PMSM, with balanced performance across each category.

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  • Xu Zhang, Jianfeng Mao, Fujiong Zhao, Weigang Wang, Rongsheng Jia
    Subject Area: Power devices and circuits
    Article ID: 21.20240088
    Published: 2024
    Advance online publication: March 12, 2024
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    In order to reduce the performance deterioration of the control system of surface-mounted permanent magnet synchronous motor (SPMSM) under the influence of external disturbances, parameter changes and other factors, a new active disturbance rejection sliding mode control strategy (ADR-SMC) based on active disturbance rejection control (ADRC) is proposed. Firstly, based on the speed-current compound loop mathematical model of SPMSM, a nonlinear active disturbance rejection controller (NLADRC) is established to observe internal and external disturbances. Secondly, based on the independent characteristics of each module of NLADRC, a sliding mode error feedback control law with fast convergence speed and strong robustness is designed to replace the NLSEF module by using the characteristics of sliding mode control (SMC) with low requirements and strong robustness for the system model. Then, the sliding mode error feedback control law is updated in real time according to the internal disturbance estimated by the extended state observer (ESO). The resulting ADR-SMC improves the dynamic response capability of the system and improves the robustness of the system to internal and external disturbances. The stability of ADR-SMC compound closed-loop SPMSM control system is proved by Lyapunov theory. Finally, the effectiveness and superiority of the proposed control strategy are verified by experimental results.

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  • Guangyin Shi, Zhiqiang Li, Lu Liu, Zhiwei Dai, Zhongmao Li, Zhe Hou, S ...
    Subject Area: Integrated circuits
    Article ID: 21.20240109
    Published: 2024
    Advance online publication: March 12, 2024
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    This letter presents a 6-bit passive vector-modulated phase shifter (VMPS) using nonlinear complementary voltage control, which is implemented in a 45-nm silicon-on-insulator (SOI) technology. The proposed passive VMPS uses a simplified, compact, low-loss transformer-based coupler to generate highly balanced orthogonal signals. The amplitude controller is implemented with only four transistors and is controlled by nonlinear complementary voltage, which greatly improves the available state rate and the accuracy of the phase shifter. The measured VMPS achieves a rms phase/gain error of 1.6°/0.35 dB with only 0.55 mm2 chip area in 20-24 GHz and no power consumption.

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  • Yong Liu, Mao Li, Deli Zhang, Feilong Jiang, Yajun Zhao, Feifei Bu
    Subject Area: Energy harvesting devices, circuits and modules
    Article ID: 21.20240091
    Published: 2024
    Advance online publication: March 11, 2024
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    Aiming at the increasing demand for the load power of more electric aircraft, this paper proposes an energy storage system based on battery. Through the modeling of the battery and the analysis of the charging and discharging characteristics, combined with the various working conditions of the aircraft, a complete energy management strategy is designed to realize the coordinated operation of the energy storage system and the generator. Finally, a semi-physical simulation platform is built based on Plecs RT Box, and the feasibility of the proposed scheme is verified by experiments.

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  • Huaiyu Zhai, Hanbo Jia, Xuan Guo, Zilin Jiang, Yuzhen Zhang, Dandan Wa ...
    Subject Area: Integrated circuits
    Article ID: 21.20240121
    Published: 2024
    Advance online publication: March 11, 2024
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    In this paper, a complementary dithering technique is proposed which utilizes LMS digital background calibration method to correct the interstage gain errors in pipeline analog-to-digital converters (ADCs). It not only has a better scattering effect on spectral spurs but also eliminates the increment of residual amplitude caused by dither injection, which will greatly alleviate the design requirements of residual amplifier. Simultaneously, the comparator resolving time nature is utilized to construct calibration windows, which averts the use of duplicate comparators and its digital logic is simple. Behavioral simulation results of 12-bit, 1.25 GS/s pipelined ADC manifest that the proposed calibration technique enhances SNDR and SFDR from 44.27dB and 49.43dB to 70.8dB and 115.3dB respectively.

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  • Xiaodan Zhou, Weipeng He, Dongbing Fu, Jianan Wang, Guangbing Chen
    Subject Area: Integrated circuits
    Article ID: 21.20240038
    Published: 2024
    Advance online publication: March 08, 2024
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    This paper presents a 14-bit 125MS/s pipeline analog-to-digital (ADC) which can be used for communication systems, especially in radar and navigation fields. A high-speed sample-and-hold amplifier (SHA) with a high-linearity bootstrapped switch has been integrated into the ADC to remove the aperture error. To improve the gain bandwidth product of amplifiers, a hybrid 1.8V/3.3V MOSFET technique is proposed, wherein 1.8V MOSFETs are used together with 3.3V devices under a 3.3V supply to utilize the higher intrinsic frequency of the 1.8V MOSFET. Meanwhile, a special bias circuit is designed to guarantee the voltage of each terminal pair of 1.8V devices will not exceed its limit value. The ADC is implemented in 0.18μm 1.8V/3.3V CMOS technology and achieves 72.1dB signal-to-noise ratio (SNR) and 92.6dB spur-free dynamic range (SFDR) with 10.1MHz sine input under 3.3V supply, while consuming 272mW power at 125MS/s. The results show that the ADC is suitable for applications where high-speed and high-resolution devices are required.

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  • Quan Xia, Gen Li, Changcun Han, Wei Zou
    Subject Area: Integrated circuits
    Article ID: 21.20240050
    Published: 2024
    Advance online publication: March 08, 2024
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    In the 0.35 um BCD process, a low-temperature coefficient, high PSRR bandgap voltage reference with high-order curvature compensation is designed. The circuit is simulated and verified using Cadence software. The results indicate that, operating with a power supply voltage of 3.3 V, and functioning across temperatures ranging from -55°C to +125°C, the temperature coefficient of the output reference voltage is 1.064 ppm/°C, the output bandgap reference voltage is 1.227 V, and the power supply rejection ratio of the circuit at a low frequency of 100 Hz is -89 dB. This illustrates that the circuit achieves a favorable balance in temperature coefficient and PSRR, demonstrating its practical utility.

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  • Xue Su, Yanhu Huang, Tiejun Chen
    Subject Area: THz devices, circuits and modules
    Article ID: 21.20240105
    Published: 2024
    Advance online publication: March 08, 2024
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    A metasurface which can realize switching between transmission and reflection modes by changing temperature is proposed. The metasurface consists of a dielectric layer and two metal layers with an extremely low profile. At low temperature, it can convert the incident circularly polarized wave into an orthogonal polarization wave; while at high temperature, the incident circularly polarized wave will be completely reflected and keep the same polarization. By appropriately arranging the unit cell structure, a full space focusing lens is realized at 1.0 THz. This work provides a new idea for designing full-space metasurfaces, which has great potential value in the fields of reconfigurable and dynamically controllable device design.

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  • Toru Sai, Yasuhiro Sugimoto
    Subject Area: Power devices and circuits
    Article ID: 21.20240106
    Published: 2024
    Advance online publication: March 08, 2024
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    A 4-coil boost DC-DC converter circuit with a large voltage gain and high output power is proposed. The target application is the 400 V DC microgrid, and the converter boosts a 20 V photovoltaic (PV) module voltage directly to the 400 V microgrid voltage using the multiphase control scheme. Four coils in 4 different clock phases are used to drive 3 parallel series-capacitor boost converters. Only one-fourth and one-half of the output voltage is required for the reverse bias voltage of transistor switches and diodes, respectively, and reliability problems are avoided. The proposed converter circuit was SPICE simulated using device parameters from commercially available transistors and diodes, and from inductors and capacitors with parasitic components. Simulation results indicate that 1.5 A and a 370 V of the output current and voltage, respectively, are obtained with more than 90 % of power efficiency. The device count of the circuit was only 16.

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  • Hua Xu, Xuqiang Zheng, Zedong Wang, Chen Cai, Wenxiang Zhen, Guojun Yu ...
    Subject Area: Integrated circuits
    Article ID: 21.20240104
    Published: 2024
    Advance online publication: March 06, 2024
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    This article presents a high-output-swing 64-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter, in which a 4-tap hybrid feed-forward equalizer (FFE) employing both fractionally-spaced pre-emphasis (FS-PE) and baud-spaced de-emphasis (BS-DE) is proposed. The PE technique enlarges the output swing by directly stacking pre-distortion pulses, and naturally consumes less power as it boosts only the desired symbols. The FS-based pre/post1 taps equalize the high-frequency loss, provide a wide compensation range beyond the Nyquist frequency, and realize a flexible equalization capability, while the BS-DE-based post2 tap compensates for the low-frequency channel loss. Fabricated in a 28-nm CMOS process, the 64-Gb/s transmitter obtains a differential output swing of 1.4 Vppd with an energy efficiency of 1.53 pJ/bit.

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  • Jian Guan, Xingyu Jiang, Ningbo Liu, Hao Ding, Yong Huang, Tong Liu
    Subject Area: Microwave and millimeter wave devices, circuits, and modules
    Article ID: 21.20240029
    Published: 2024
    Advance online publication: March 05, 2024
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    Effectively harnessing the correlation information within data through the covariance matrix, a geometrically informed matrix constant false alarm detector proves proficient in target detection amidst sea clutter, employing a limited number of millimeter-wave pulses. However, current matrix CFAR detectors solely rely on a single data channel, exhibiting high computational complexity, thus resulting in diminished utilization of correlation information and constrained detection scenarios. This letter proposes a low-complexity detector based on the maximum eigenvalue derived from dual-channel data. Leveraging Fast Fourier Transform, the authors preprocess data from two channels, construct eigenvalues of the cross-covariance matrix to capture correlations, and employ the maximum eigenvalue as the detection statistic, subsequently devising a matrix CFAR detector based on this dual-channel maximum eigenvalue suitable for practical scenarios. In addition, the detector is verified to achieve better practical detection performance with the measured sea clutter data.

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  • Li Cheng
    Subject Area: Circuits and modules for electronic instrumentation
    Article ID: 21.20240068
    Published: 2024
    Advance online publication: March 05, 2024
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    In a GNSS receiver, carrier tracking is the most challenging part, especially in a harsh environment. This paper presents an open tracking loop structure to overcome the matter of losing lock under weak-signal conditions. In order to enhance the stability and sensitivity of weak GNSS signal tracking, a frequency-locked loop structure based on DFT interpolated frequency estimation is proposed. The IF signals are split into two branches in the structure, and each signal is correlated with an equally frequency-spaced local carrier. Then, a new DFT interpolation algorithm of two-point DFT interpolation is used as a frequency discriminator to calculate the carrier frequency deviation. The bias and RMSE performances of the frequency discriminator are comparatively analyzed under different SNRs using computer simulations. Simulation results show that this discriminator is characterized by small computational effort and high estimation accuracy. The signal-tracking performances of the structure are verified by an experiment using a GNSS simulator. Results demonstrate that this method is able to track 26 dB-Hz signals using only 8 samples, which improves the tracking threshold by 4 dB-Hz over the FFT discriminator, and its tracking error jitter is less than 0.5 Hz. The structure needs only two-point interpolation, resulting in a low computation load in a real-time receiver.

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  • Yue Xu, Jie Xie, Dongmin Wu
    Subject Area: Integrated optoelectronics
    Article ID: 21.20240077
    Published: 2024
    Advance online publication: March 04, 2024
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    The inherent characteristics of Micro Electro Mechanical Systems (MEMS) mirrors are subject to change due to operational conditions and usage duration. Currently, most methods for driving, detecting, and compensating electromagnetic MEMS mirrors require complex modules. This paper introduces an approach based almost entirely on Field Programmable Gate Array (FPGA). The proposed method involves the construction of a Direct Digital Synthesizer (DDS) with adjustable frequency, amplitude and phase, a high-precision digital cross-correlation detector, and a proportion integration differentiation (PID) compensator based on FPGA. The system does not necessitate stringent external module requirements and is capable of achieving precise detection and stable operation of the rotation angle of MEMS mirrors.

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  • Hao Li, Zhao Yang, Dezhu Kong, Aiguo Yin, Jibing Peng, Peiyong Zhang
    Subject Area: Integrated circuits
    Article ID: 21.20240055
    Published: 2024
    Advance online publication: March 01, 2024
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    This letter presents an 840µm2 557nW temperature sensor front-end designed for system on chip (SoC) thermal monitoring. The circuit is implemented using MOS transistors exclusively, which enhances its scalability with process technologies and compatibility with digital circuit processes. To address MOSFETs circuit’s process variation issues, a differential voltage readout scheme is employed. Dynamic element matching (DEM) is used to minimize mismatch of the circuit. The sensor is self-referenced, eliminating the need for an external reference voltage. Real-time voltage calibration (RVC) scheme is used to improve the performance of supply sensitivity. It is fabricated using a 55nm process, and the measurement results showed an error of -0.69/0.85℃ across 16 samples over a temperature range of 0℃ to 100℃ with a low-cost one-point calibration at 30℃, while the maximum supply sensitivity is 3.3℃/V.

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  • Yangyan Lv, Sheng Xie, Guoxuan Qin, Luhong Mao, Ruiliang Song, Naibai ...
    Subject Area: Integrated circuits
    Article ID: 21.20240059
    Published: 2024
    Advance online publication: March 01, 2024
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    Aiming at the jitter issue in four-level pulse amplitude modulation (PAM4) receive link, the key causes related to the non-ideal effects of channel and data decision were analyzed, and a modified PAM4 receiver architecture was proposed. An analog equalizer with extra mid-frequency compensation and 1-tap decision-feedback equalizer were incorporated to minimize the inter-symbol interference. To alleviate the timing constraints in DFE, the feedback loop of slicer was optimized. The post-simulation results based on TSMC 28 nm CMOS process indicate that the proposed 50 Gb/s PAM4 receiver functions well over a channel with 12 dB loss at Nyquist frequency. The peak-to-peak jitters of two restored NRZ signals are 1.5 ps and 2.5 ps, respectively.

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  • Kodai Nakamura, Takanori Sato, Kunimasa Saitoh
    Subject Area: Optical hardware
    Article ID: 21.20240065
    Published: 2024
    Advance online publication: March 01, 2024
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    A silicon mode multiplexer (MUX) based on the three-stage cascaded wavelength insensitive coupler (3CWINC) is proposed and numerically demonstrated. The 3CWINC is composed of three identical asymmetric directional couplers (ADCs) and two different phase adjustment regions placed between each ADC. We numerically show that high-performance mode MUX is easily designed using 3CWINC, which consists of ADC with transmission higher than 25% over the entire operating wavelength range. The designed TE0-TE1 mode MUX based on 3CWINC can maintain transmission 94.4% (−0.25 dB) or higher even if fabrication error of waveguide width occurs up to 10 nm.

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  • Shaohao Wang, Xiangjie Ding, Ying Yang
    Subject Area: Integrated circuits
    Article ID: 21.20240057
    Published: 2024
    Advance online publication: February 29, 2024
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    To improve the tracking processing speed of embedded Global Navigation Satellite System (GNSS) receivers, we propose seven custom instructions and a tracking accelerator integrated into the self-developed 32-bit RISC-V processor named Prism. The accelerator can increase execution speed significantly at a reasonable area and power cost. The FPGA test and synthesis under the 40nm technology showed that the accelerator achieved 58% to 94% speed increase for three tracking loops, and 122% to 700% speed increase for seven custom instructions, at the cost of 33.1% more area and 19.8% more power consumption.

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  • Zeng Zhibin, Chen Yu, Qu He, Lou Yongchen, Bai Lei
    Subject Area: Integrated circuits
    Article ID: 21.20240004
    Published: 2024
    Advance online publication: February 28, 2024
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    Aiming at the demand for FPGA-based high-bandwidth NVMe SSD host access, this letter presents an NVMe over PCIe Hardware Acceleration Engine (NoPHAE), which has two innovative aspects. Firstly, an NVMe Queues Engine is integrated into the NoPHAE to enhance I/O performance and reduce resource consumption. The NVMe Queues Engine provides dynamic queue configuration and introduces a virtual completion queue, which reduces resource consumption by 20%. Secondly, a PCIe Acceleration Engine is built in the NoPHAE, which implements the co-design of PCIe and NVMe and optimizes the timing for processing PCIe transport layer transactions, resulting in a significant increase in data throughput. Test results indicate that the sequential read and write speed of the NoPHAE is 7.93 times faster than that of the baseline, and the random read and write performance is two times faster than that of the baseline.

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  • Junjia Su, Yihao Chen, Pengcheng Feng, Zhelong Jiang, Zhigang Li, Gang ...
    Subject Area: Integrated circuits
    Article ID: 21.20240071
    Published: 2024
    Advance online publication: February 28, 2024
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    Medical industry increasingly using convolutional neural networks (CNNs) for image processing. Nowadays, computing facilities based on Von Neumann architecture aredevoted to accelarate CNNs, yet rapidly hitting a bottlenneck in performance and energy efficiency. The computing-in-memory (CIM) architecture based on random-access memory (ReRAM) emerged as a method to overcome the issue. This work proposes a charge-domain one-transistor-one-resistor-one-capacitor (1T1R1C) CIM macro using energy-efficient charge calculation and capacitive coupling for CNNs acceleration in medical semantic segmentation. The multiplication-and-accumulation (MAC) is realized by charge distribution with a cell and capacitive coupling across different cells on a plate line. The configurable output resolution is achieved by on-chip ReRAM-based charge integral, which is energy efficient and flexible to change the output resolution. By evaluation in the 180nm technology, the proposed macro with a 64×64 array achieves a peak energy efficiency of 142.2 GOPS/W, ∼1.3X higher than previous work. The inference dice coefficient of UNet reaches 89.7%.

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  • Hao Li, Guobin Yang, Chunhua Jiang, Tongxin Liu, Chongzhe Lao
    Subject Area: Integrated circuits
    Article ID: 21.20240002
    Published: 2024
    Advance online publication: February 27, 2024
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    The Wuhan Ionospheric Sounding System (WISS), based on FPGA and DDS architecture with USB communication, was developed for studying the ionosphere by the Ionospheric Laboratory of Wuhan University. This letter presents an improved hardware system of WISS, which is based on network port communication and suitable for software defined radio. The output waveforms are more controllable and more diversified in the improved system than the previous version. The new version of ionospheric sounding system can not only conduct conventional ionospheric exploration, but also implement meteors sounding by VHF band. The system structure and the design scheme of each module are described in detail. Then, some typical experiment results are carried out to verify the performance of the improved system. Results show that the new version system performed well in the experiments of ionospheric meteors sounding.

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  • Junyi Luo, Zhiwei Zhang, Xuefei Xuan, Chao Gu
    Subject Area: Microwave and millimeter wave devices, circuits, and modules
    Article ID: 21.20240044
    Published: 2024
    Advance online publication: February 26, 2024
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    This paper proposes a methodology to design broadband high-efficiency power amplifiers. A novel continuous mode is proposed through combination the continuous class-F mode and the traditional class-EF mode under certain conditions. Thus, the advantages of wide bandwidth and high efficiency can be integrated into one power amplifier, that is, the proposed continuous mode class-EF power amplifier mode. In order to verify the effectiveness of the proposed method, a broadband high-efficiency power amplifier operating at 1.5-3.0 GHz is designed and implemented based on the CGH40010F GaN transistor. Measurements indicate that the saturated output power is greater than 40.2 dBm, drain efficiency is between 63% and 70%, gain exceeds 10 dB, across the whole frequency range.

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  • Yang Xiao, Zhongyuan Zhou, Changping Tang, Jinjing Ren, Shikuan Liu
    Subject Area: Electron devices, circuits and modules
    Article ID: 21.20230573
    Published: 2024
    Advance online publication: February 22, 2024
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    In order to study the coupling mechanism of the transient immunity of digital control circuits, the equipment of digital control circuits is developed in order to obtain a general method of modeling and simulation of the transient immunity. The power module of the digital control circuit is its basic function module. This paper extracts the characteristic parameters of the EMI coupling path of the digital control circuit and establishes an equivalent circuit, based on the established RFI-based power module conductive immunity model. A method of port response simulation for power module of digital control circuit under transient interference based on transfer function and segmental circuit simulation is proposed. This method has a certain value for studying the coupling mechanism of conductive interference.

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  • Bin Fang, Huakang Xia, Guozhu Chen, Yinshui Xia, Ge Shi, Yidie Ye, Xiu ...
    Subject Area: Energy harvesting devices, circuits and modules
    Article ID: 21.20240084
    Published: 2024
    Advance online publication: February 22, 2024
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    Piezoelectric transducers (PZTs) can be used not only for vibration energy harvesting (VEH), but also for vibration signal sensing. However, it is difficult to realize both functions on a single PZT. In this paper, we propose a simultaneous energy harvesting and acceleration measuring (SEHAM) solution based on a single PZT. It is implemented by time-space sharing strategy rather than time-division multiplexing strategy. In addition, a signal extraction model based on first harmonic approximation (FHA) method is established to recover acceleration signals from SEHAM operations. Finally, a rapid prototype is built to evaluate the performance of SEHAM under different vibration frequencies. Experimental results show that the EH and AM operations can be carried out simultaneously. At the resonance point, the average relative error of AM is 7.14%, and the EH power is 189.10µW with a PZT open-circuit voltage of 5V. This solution is significant to the development of self-powered sensors and can be used as redundant backup of traditional sensors.

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  • Koki Sone, Hiroyuki Torikai
    Subject Area: Devices, circuits and hardware for IoT and biomedical applications
    Article ID: 21.20240036
    Published: 2024
    Advance online publication: February 21, 2024
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    In this paper, a novel design of an ergodic sequential logic cochlear single partition model, which can reproduce a typical nonlinear sound processing function (so-called nonlinear compression) of a mammalian cochlea, is proposed. Analyses show that the model can reproduce fundamental characteristics of the nonlinear compression of the mammalian cochlea. In addition, the model is implemented by a field programmable gate array, and its operation is verified by experiments. It is then shown that the model can be implemented with fewer circuit elements and consumes lower power compared to a standard ordinary differential equation cochlear model. Finally, it is discussed that the results of this paper will be useful in developing a small and low-power cochlear implant that can reproduce nonlinear sound processing functions of the human cochlea.

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  • Zaichao Yang, Li Xu, Hao Wang, Bin Li
    Subject Area: Electromagnetic theory
    Article ID: 21.20240025
    Published: 2024
    Advance online publication: February 20, 2024
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    We are concerned with the numerical simulation of metasurfaces modeled by generalized sheet transition conditions (GSTCs). A hybridizable discontinuous Galerkin (HDG) method is pro-posed to treat the field discontinuity on the metasurface. We briefly recall the mathematical expressions of the surface susceptibility tensors and present the formulations of the HDG method. The numerical examples by simulating monoanisotropic metasurface show that the proposed HDG method can easily adapt to the discontinuities caused by GSTCs. Additionally, we present COMSOL simulation results for the same metasurface to further validate the efficacy of the proposed method.

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  • Jiajian Pei, Ping Sun, Shijun Li, Yao Xiao, Jianfeng Cai
    Subject Area: Integrated circuits
    Article ID: 21.20230640
    Published: 2024
    Advance online publication: February 16, 2024
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    A low-dropout voltage linear regulator with low quiescent current and high PSR over a wide frequency range is designed to meet the application requirements of high-performance CMOS image sensor. An embedded impedance attenuation buffer is proposed to embed the feedforward path into the buffer, reduce the quiescent current and improve PSR in a wide frequency range. The simulation result shows that LDO achieves a PSR better than 60dB up to 10MHz for load current up to 100mA. The LDO achieves 65dB PSR at 1MHz and 90dB PSR at 1KHz. LDO consumes a quiescent current of 36uA with a bandgap reference circuit included.

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  • Zhen Mao, Bing Li, Linning Peng, Yuanzhong Li
    Subject Area: Integrated circuits
    Article ID: 21.20240013
    Published: 2024
    Advance online publication: February 16, 2024
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    This paper presents a compact IDELAY-based PUF technology, which utilizes Xilinx FPGA IO-Block's IDELAY tap delay values to generate a unique and secret key. IDELAY-RO generates a counting-pulse input by replacing the inverters in the Ring Oscillator (RO) and developing it over a fixed time to produce a corresponding dataset in ZYNQ PSoC's Programmable Logic (PL). Polynomial regression is fitted to the dataset and compared with the raw data to create a 31-bit bitstring in the Processing System (PS) of ZYNQ PSoC. Our analysis of thirty XC7Z010CLG400-1 chips revealed that the IDELAY-RO PUF has a reliability of 98.23% and uniqueness of 49.63%, with 59.38% uniformity, using fewer FPGA resources.

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  • Kunbo Cao, Yong Xu, Wenqi Li, Jiayu Wang, Wandi Lu, Ziyue Li
    Subject Area: Energy harvesting devices, circuits and modules
    Article ID: 21.20240032
    Published: 2024
    Advance online publication: February 16, 2024
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    A novel miniaturized fourth order Hilbert fractal rectifier antenna for collecting ultra-short wave RF electromagnetic energy is proposed. The receiving antenna is miniaturized by using the fourth-order Hilbert fractal structure and the slow-wave cross-finger structure, with antenna sizes of 274.86mm × 144.38mm, seven resonances are excited and form a wideband, which locates at 100-300MHz. In the rectifier part, the third order voltage doubling rectifier circuit is designed, which is composed of three sets of Schottky diodes and filter capacitors. The maximum rectification efficiency of this circuit is greater than 80% in simulation and 78% in measurement. The experimental results show that the rectifier antenna has great potential to collect energy in the electromagnetic environment with abundant ultrashort wave energy.

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  • He Li, Jiapeng Zhao, Qianqi Zhao, Xu-Feng Cheng
    Subject Area: Electron devices, circuits and modules
    Article ID: 21.20240037
    Published: 2024
    Advance online publication: February 15, 2024
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    This paper proposes a novel quadratic boost converter(QBC) based ultra-high gain DC-DC converter with coupled inductor(CI) and voltage multiplier cells(VMC). Based on the structure of this converter, the energy leaked through the coupled inductor can be recycled and transferred to the output to improve the voltage gain. Meanwhile, it has the common ground characteristics and good static output stability. The converter is tested for an application requiring the output power of 50 W∼300 W, operating with 25 V input voltage and 547 V output voltage, and it has the voltage gain of 21.8 under the medium and low duty cycle, the peak efficiency is 92.5%.

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  • Wu Jianyu, Xu Mengdi, Zheng Yifei, Zhang Hongli, Xu Hao
    Subject Area: Integrated circuits
    Article ID: 21.20230634
    Published: 2024
    Advance online publication: February 06, 2024
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    Due to the low noise and high linearity characteristics of GaAs Hetero-junction Bipolar Transistors (HBTs), Low Noise Amplifiers (LNAs) are widely used in aerospace, communication, computer, and other fields. Extracting device model parameters is of great significance for subsequent research on the electromagnetic compatibility characteristics of such devices. In this paper, based on the small signal model, the model parameters of the amplifier are extracted by combining the I-V characteristics of the amplifier under different external voltage conditions. The linear model parameters are extracted using a fitting analysis method to obtain the Pspice circuit model of the GaAs amplifier under normal operating conditions. The simulation results align closely with the measured results. Compared with traditional modeling methods, this approach effectively resolves the issue of being unable to measure parameters due to chip packaging. This method holds substantial significance in extracting circuit model parameters and conducting in-depth research on circuit electromagnetic compatibility characteristics of this device.

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  • Zeyu Wang, Makoto Ikeda
    Subject Area: Integrated circuits
    Article ID: 21.20230628
    Published: 2024
    Advance online publication: January 24, 2024
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    Homomorphic Encryption (HE) has become a promising technique to protect the data privacy in cloud computing, while its slow speed highly restricts the application. We propose a high throughput and fully pipelined implementation of ciphertext multiplier on FPGA to accelerate ciphertext multiplication, which is one of the frequently performed operations in HE applications and takes most of the calculation time. The fully pipelined architecture avoids memory access conflict and minimizes the memory usage on chip. Consequently, the logic cells, including LUTs and DSPs, are efficiently utilized for high parallelism degree and high throughput is achieved. The throughput is increased to 4.7 times compared to state-of-art FPGA designs and 1340 times of CPU performance.

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  • Jiarui Ren, Yue Zhao
    Subject Area: Integrated circuits
    Article ID: 21.20230598
    Published: 2024
    Advance online publication: January 10, 2024
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    This paper presents a bandgap reference (BGR) circuit with high precision and low power, which is suitable for wide supply and temperature range DC-DC converters. A thermal compensation method is designed to improve output accuracy. A thermal shutdown detection (TSD) circuit is proposed to prevent overheating. It also adopts a two-channel pre-regulator, which reduces the current consumption and area while enhancing PSRR. The measured results show the temperature coefficient (TC) stands at 5.69 ppm/°C in the range of -40°C to 155°C. The typical current consumption is 0.84μA in the supply range from 3.5 to 40 V. The PSRR is -86dB at 1kHz.

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  • Hong-yin Zhang, Hong-chao Wu, Zhen Wang, Tian Li
    Subject Area: Microwave and millimeter wave devices, circuits, and modules
    Article ID: 20.20230519
    Published: 2023
    Advance online publication: December 01, 2023
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    A wideband crossed dipole antenna for dual-polarized applications is presented in this paper. The antenna consists of a printed crossed dipole radiator loaded with periodic slots, four metal posts, four metal sidewalls and a metal reflector. The crossed dipole antenna is directly fed by a simple coaxial cable, achieving stable dual-polarization radiation characteristics. Here, two approaches are adopted to adjust the high and low resonant frequency of the antenna with large freedom. Firstly, four metal posts are introduced into conventional crossed dipole antenna, and their distance from the feeding point can independently adjust the lower resonant mode. Secondly, periodic slots are etched on the crossed dipole arms, and the upper resonant frequency can be controlled independently by altering the length of these slots. Also, the metal sidewalls on the ground are used herein to obtain enhanced gain property. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The measured results show good performance of a relative bandwidth of 64.3% for VSWR ≤ 2 (1.32-2.57 GHz). Moreover, the antenna has good unidirectional radiation performance and can achieve maximum gain of 9.1 dBi at 2.3 GHz.

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  • Bu-Lai Wang, Ye-Cheng Li, Zi-Xin Li, Jing-Heng Zhu
    Subject Area: Power devices and circuits
    Article ID: 20.20230483
    Published: 2023
    Advance online publication: November 24, 2023
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    In order to solve the problems of the traditional model reference adaptive system (MRAS) speed estimation adaptive mechanism, such as poor tracking accuracy and slow response, A new dual sliding mode adaptive observer is designed to estimate the rotational speed and rotor position of permanent magnet synchronous motor (PMSM). Firstly, a new two-variable complex reaching law is used to replace the traditional first-order sliding mode for velocity loop control, and an anti-saturation scheme is introduced to improve the anti-interference ability of the system. Secondly, the PI adaptive mechanism in the traditional MRAS is replaced by a new super-twisting weighted integral type algorithm adaptive observer (STWITA-AO), which effectively speeds up the convergence of the estimated speed and reduces the inherent chattering of the sliding mode structure. Finally, the relevant simulation is compared and verified. The simulation results show that the estimation strategy based on the new double sliding mode MRAS control can make the speed estimate converge to the actual value faster, and improve the dynamic performance and robustness of the observer.

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  • Qingzhi Zhu, Lin Xu
    Subject Area: Electromagnetic theory
    Article ID: 20.20230430
    Published: 2023
    Advance online publication: October 06, 2023
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    The novel rare earth variable flux permanent magnet synchronous motor (PMSM) for electric vehicles is proposed. The structure and magnetic field regulation characteristics are analyzed, the variation of magnetic density, no-load back electromagnetic force and output torque with speed was studied through finite element simulation. The weak magnetic field expansion speed performance of the novel PMSM has been verified through experimental equipment. The adjustable electromagnetic field with running speed on the rare earth PMSM increases the high-speed operation range of vehicle.

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  • Hong-yin Zhang, Hong-chao Wu, Zhen Wang, Tian Li
    Subject Area: Microwave and millimeter wave devices, circuits, and modules
    Article ID: 20.20230388
    Published: 2023
    Advance online publication: August 31, 2023
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    A wideband dual-line polarized antenna with low-profile property is presented in this paper. The dual-polarized antenna consists of two crossed antenna elements over a metal reflector and is excited by RF connectors vertically. Here, the crossed antenna element is based on Vivaldi radiator to obtain wideband performance. By loading resistors on the patches of Vivaldi radiator, not only the impedance matching of the proposed antenna can be improved further but also the profile is reduced greatly. Whatever, the loaded resistors can also depress radiation efficiency of the antenna element to a certain extent, especially in the lower band. For this reason, three periodic slots etched on the Vivaldi radiator are introduced herein to enhance the gain performance. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The results show good performance of a relative bandwidth of 153% for VSWR ≤ 2 (2-15 GHz) and a low profile of 0.22 λL (in terms of the lowest frequency of the band). Besides, the prototype can achieve an average gain of approximately 5 dBi and a maximum radiation efficiency of 80% within passband.

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  • Changtian Xu, Yanan Zhang, Xingwu Yang, Zhicheng Meng
    Subject Area: Power devices and circuits
    Article ID: 20.20230181
    Published: 2023
    Advance online publication: August 04, 2023
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    Level-increased nearest level modulation (NLM) has been widely used in the modular multilevel converter (MMC) due to its simple implementation and low switching frequency in recent years. However, there are some disadvantages such as the poor performance of output voltage distortion and harmonic circulating current. A harmonic circulating current (CC) suppression method based on level-increased NLM is proposed in this paper. The impact of level-increased NLM on the CC is firstly analyzed. Then, a 5-voltage-level compensation method for harmonic CC suppression is proposed. Simulation and experiment verify the effectiveness of the proposed method.

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  • Luning Xiao, Wenxiang Zhen, Yongbo Su, Zhi Jin
    Subject Area: Microwave and millimeter wave devices, circuits, and modules
    Article ID: 20.20230191
    Published: 2023
    Advance online publication: May 25, 2023
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    A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( fT). Broadband operation is achieved using an enhanced degenerated Darlington fT-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional fT-doubler structures, the enhanced cascode Darlington fT-doubler structure reduces the “VCE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher VCE for amplifying transistors, which represents higher fT,peak performance. Benefiting from the proposed Darlington fT-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181- fT bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

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  • Haiyang Xia, Tao Zhang, Zhiqiang Liu, Huan Liu, Xu Wu, Lianming Li, Zh ...
    Subject Area: Microwave and millimeter wave devices, circuits, and modules
    Article ID: 20.20230094
    Published: 2023
    Advance online publication: May 18, 2023
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    This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

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  • Jie Yang, Hong Fan
    Subject Area: Power devices and circuits
    Article ID: 20.20230009
    Published: 2023
    Advance online publication: February 24, 2023
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    To improve the dynamic response performance and robustness of a permanent magnet linear synchronous motor (PMLSM)-based servo system, an adaptive proportional-integral-derivative (PID) controller based on a particle swarm optimization neural network is proposed. First, according to the mechanical dynamics equation of the PMLSM, a mathematical model of the PMLSM was established. Second, an adaptive PID speed controller is designed to realize real-time control of the PMLSM. To improve the dynamic performance and stability of the controller, a particle swarm optimization neural network is used to dynamically tune the parameters. Finally, the effectiveness of the proposed controller was verified on the MATLAB/Simulink simulation platform. Compared to the traditional PID controller, the adaptive PID controller can improve the dynamic performance of the system more effectively.

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  • Yinyi Zhu, Haitao Sun, Mingzhi Shao, Ruihao Wang, Zhenyu Zhao, Yan Che ...
    Subject Area: Power devices and circuits
    Article ID: 19.20220488
    Published: 2022
    Advance online publication: December 09, 2022
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    A novel buck-boost power converter is proposed to improve the performance of switched reluctance generator (SRG) system in an electric vehicle. In the proposed topology, the energy conversion part is formed by a buck-boost circuit and additional switches, with which, it is flexible to significantly boost the magnetization voltage and demagnetization voltage, thereby the output power range is improved and the power losses are reduced. The basic structure of the proposed converter is presented first and the attached operating modes are analyzed. The control strategy of the SRG system is then made to control the output voltage and the boost capacitor voltage. The simulation results show that compared to the conventional buck-boost converter, the proposed converter enhances the efficiency and reduces the power losses.

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  • Yingxiang Gong, Zile Fan
    Subject Area: Devices, circuits and hardware for IoT and biomedical applications
    Article ID: 19.20220431
    Published: 2022
    Advance online publication: October 18, 2022
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    How to replace the referee in sports with artificial intelligence has attacked a huge amount of attention recently. In this paper, non-battery pressure detection and communication system are designed and fabricated aiming to help the referee in the basketball games. To get the information from player and ball at the same time, the designed system is consisted of three parts, including the basketball monitoring system, the shoes monitoring system, and the laptop to collect and process the data. For the basketball monitoring system, eight piezoelectric polyvinylidene fluoride (PVDF) flexible thin films are used as the sensor on the surface of the basketball with the sensitivity of 0.065 V/N and four hard piezoelectric Lead Zirconium titanite (PZT) patches are set inside the ball as the power source. As for the shoes monitoring system, four PZT patches work as both power source and pressure sensor with a sensitivity of 0.025 V/N. To solve the referee problem in basketball game, time delay of different systems is first measured. The different systems have similar time delay of about 3s, which will help to make sure whether the players break the rules. In this paper, whether the player has a traveling violation in a game can be refereed by the collected data, which has more than 97% accuracy. This work shows an innovative progress in automatic referees in games and the Internet of Things (IoT) in the human health monitoring.

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  • Hao Liu, Ming-Jiang Wang, Ming Liu
    Subject Area: Integrated circuits
    Article ID: 18.20210335
    Published: 2021
    Advance online publication: September 15, 2021
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    Approximate computing has excellent result in error-tolerant applications sacrificing computational accuracy for better performance in the area, speed, and power consumption. As the most basic operation, addition is used in a large number of applications in various occasions. Therefore it is of great importance to optimize the performance of addition computation. In this paper, a segemented carry prediction adder (SCPA) structure is proposed, which splits the long carry chain into several short chains for parallel computation. The design parameters are diversified by adjusting the size of the blocks and the prediction depth of each subadditive to achieve different levels of performance. Flexible parameter tuning allows different design goals to be achieved based on specific performance requirements, which makes SCPA a useful design guideline for approximate adders. The error performance of SCPA is mesured by MRED, NMRED, ER, and other indicators and significantly has the best statiscal performace compared to similar designs. The proposed design is synthesized under TSMC 65nm process, and the result shows that the SCPA has a very nice accuracy-power tradeoff under 8-bit and 16-bit condition.

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  • Xin Jin, Ningmei Yu
    Subject Area: Integrated circuits
    Article ID: 18.20210041
    Published: 2021
    Advance online publication: June 07, 2021
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    Transient execution attack does not affect the state of processor microarchitecture, which breaks the traditional definition of correct execution. It not only brings great challenges to the industrial product security, but also opens up a new research direction for the academic community. This paper proposes a defense mechanism for SMT processors against launching transient execution attacks using shared cache. The main structure includes two parts, a security shadow label and a transient execution cache. In the face of the side channel attacks widely used by transient execution attack, our defense mechanism adds a security shadow label to the memory request from the thread with high security requirement, so that the shared cache can distinguish the cache requests from different security level threads. At the same time, based on the record of security shadow label, the transient execution cache is used to preserve the historical data, so as to realize the repair of the cache state and prevent the modification of the cache state by misspeculated path from being exploited by attackers. Finally, the cache state is successfully guaranteed to be invisible to any attacker’s cache operations. This design only needs one operation similar to the normal memory access, thus reducing the memory access pressure. Compared with the existing defense schemes, our scheme can effectively prevent Spectre attack, and the overhead of performance is only 3.9%.

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