CLLC converters are widely used in bidirectional DC applications, particularly in aviation and vehicle power supplies, requiring high dynamic commutation performance. This paper presents a commutation control method for CLLC converters based on a state trajectory model. The forward and reverse state trajectory models are developed, and the optimal commutation trajectory is derived. The gate drive signal's pulse width is calculated based on the post-commutation gain. Simulations validate the proposed model's accuracy and the control method's dynamic performance, showing significant improvement over traditional linear control methods.

A fully tunable bandpass filter based on convex resonators is proposed in this letter. Independent tuning of the center frequency and bandwidth of the filter is achieved by adjusting the tunable capacitors loaded at different positions on the resonator. This tunable filter has the advantages of large design freedom, wide adjustment range, and easy cascading to improve the out of band suppression performance. To verify the proposed idea, a 3-order fully tunable bandpass filter was designed and fabricated. The measured results show that the center frequency of the fully tunable filter can be tuned in the range of 223MHz-537MHz, with a frequency variation range of 82.6%, and a 3dB bandwidth tunable in the range of 54MHz-73MHz.

Self-feedback test vector generation uses the circuit itself to generate test vectors, which greatly reduces the cost of testing without relying on other equipment. However, there are a great number of feedback nodes in the circuit, so how to select the feedback scheme is a problem. This paper proposes an adaptive matching method to select the self-feedback scheme. First, the final feedback nodes are selected by using the self-defined test vector similarity in the adaptive matching method, and then the optimal arrangement order of feedback nodes is determined by using the self-defined test vector matching degree. The self-feedback structure of the sequential circuit is improved and the number of multiplexers (MUXs) is reduced. The test vector similarity and the test vector matching degree are introduced into the parameters TR and Cr of the Spider Wasp Optimization Algorithm (SWO), respectively, so that the parameters can be adaptively adjusted in the process of selecting feedback nodes.

This article presents a 100 Gb/s four-level pulse amplitude modulation (PAM4) analog front-end (AFE) implemented in TSMC’s 28-nm CMOS process. The continuous-time linear equalizer (CTLE) employs the transconductance (GM) stage for mid-frequency (MF) peaking, while leveraging the transimpedance (TIA) stage to produce high-frequency (HF) peaking. This allows the HF peak frequency to remain constant as the boost range is adjusted. While the variable gain amplifier (VGA) employs shunt inductive peaking and feedforward technique to extend bandwidth. Both CTLE and VGA use complementary structures to improve linearity. Frequency response tests show the AFE has a 31 GHz peak frequency and a 33.1 dB gain boost. Eye diagram measurements confirm it can open eyes for 100 Gb/s PAM4 signals.

Cost aggregation is a crucial step in the accurate stereo depth estimation process known as semi-global matching. However, this step is challenged by storing large amounts of aggregated data, which is necessary to achieve high matching accuracy under large resolution and large disparity conditions. In this paper, we propose a multi-path optimization aggregation strategy and re-select the complementary combinations of key paths in the forward and backward scanning directions to improve the matching accuracy as much as possible. An error rate of only 5.21% is achieved on the KITTI 2015 dataset. Next, we propose DCT-based truncated compression and selective storage to alleviate the problem of memory increase due to the introduction of reverse critical aggregation paths. Experiments show that the matching error rate increases by only 0.6% on the KITTI 2015 dataset with 53% memory savings. Finally, 1920 × 1080 @62fps @128MHz is achieved on ZCU102 FPGA.

This paper proposes a novel topology of grain-oriented electrical steel permanent magnet synchronous motor (GO-PMSM) with spliced teeth-yoke structure for electric vehicles, aiming to address the vibration challenges under high power density demands. Two motors (GO-PMSM and NO-PMSM) with identical dimensions were designed. Through theoretical analysis and multiphysics finite element modeling, the magnetostrictive and electromagnetic force-induced vibrations were investigated. Simulations revealed that GO-PMSM exhibits 18.32% higher average torque and increased radial flux density due to anisotropic permeability. Experimental results demonstrated that the primary vibration sources are the 12th-order electromagnetic force harmonics (0th and 48th spatial orders) and the 10th/14th harmonics (8th spatial order). Notably, GO-PMSM shows significantly higher low-frequency vibration (below 1500 Hz) caused by magnetostriction in the teeth. This study highlights the trade-off between power density enhancement and vibration amplification in GO-PMSM, providing critical insights for high-performance motor design.

A V_AQ-based DAC switching scheme is proposed to improve the power efficiency of SAR ADCs. The input signals are sampled onto bottom-plates of the most significant bit (MSB) capacitors, thereby eliminating the reset energy. The reference voltage V_CM rather than V_REF is switched during the third-bit cycle, thus significantly reducing the power consumption. Additionally, an energy-efficient one-sided switching technique is employed from the fourth-bit cycle. This proposed switching scheme achieves a 99.51% reduction in switching energy over the classic scheme. The ADC with the proposed switching scheme is designed in 0.18-μm CMOS technology. It consumes 37.7 nW at a sampling rate of 20 KS/s and 0.6 V supply, and achieves the ENOB of 9.59 bits, resulting in a figure of merit (FOM) of 2.45 fJ/conversion-step.

A high-quality, high-yield integration of oriented M-type thick ferrite film with a SiC substrate through a simple and robust low-temperature thermocompression bonding technique is reported, solving the issue that ferrite devices, particularly ferrite circulators, cannot be integrated with planar RF circuits. Based on this bonding technique, a miniaturized self-biased circulator is successfully integrated onto a SiC substrate. This circulator, measuring 3.0 mm × 2.8 mm and operating at 35 GHz, exhibits a relatively low insertion loss of 1.2 dB, a bandwidth of 2.5 GHz, and a maximum isolation of 17 dB.

This paper proposes a scheme for applying space vector control method to a Switched Reluctance Generator (SRG) system with a ring winding structure. This paper focuses on the rectification system of SRG system, primarily analyzing the simulation model of the proposed system and the dual closed-loop control strategy for voltage and current. A solution has been developed to handle the strongly nonlinear and tightly coupled structure of the SRG when adopting the inner current loop control, and the issue of sector abrupt change that occurs when traditional control strategies are applied to the SRG system has been resolved. The performance of the SRG with a ring winding structure under different control strategies is compared in Simulink, verifying the effectiveness of the control strategy. Finally, the authenticity of the proposed control strategy is further validated on an experimental platform.

The edge electric field effect of the Schottky junction impacts the diode performance, limiting their application in terahertz frequency multiplier circuits. To address this problem, this paper presents a novel GaAs Schottky barrier diode(SBD) with a vertical sidewall epitaxial profile, which is fabricated by Inductively Coupled Plasmadry(ICP) dry etching. Electromagnetic simulation of the two types of SBD is also carried out to investigate the effect of structural changes on the parasitic effects. Compared to the normal structure SBD, the new design increases the reverse breakdown voltage from -7.5V to -8.4V and reduces the coupling capacitance between the metal finger and the mesa from 4.9 fF to 1.7 fF. A 170 GHz frequency doubler based on this diode demonstrates a maximum frequency doubling efficiency improvement of 4.9% over normal structure SBD, which validates the effectiveness of the SBD with a vertical sidewall epitaxial structure in enhancing the performance of frequency multipliers.

This paper designs a perovskite-metal hybrid metasurface that can independently control the phase of transmitted and reflected waves under the same incident terahertz wave, thereby achieving different wavefront functions in different electromagnetic spaces. The designed metasurface has two layers of perovskite-metal and one dielectric layer. When the perovskite is in metallic state, the metasurface works in transmission mode; when the perovskite is in insulating state, the metasurface works in reflection mode. By utilizing the geometric phase principle and the convolution principle, a four-focal-lens is realized in the transmission space, while generating a four-channel orbital angular momentum in the reflection space. This work offers potential applications in dynamic imaging, communication, and other fields.

The globalization of the semiconductor supply chain has created new challenges for security researchers. Hardware Trojans (HTs) are considered to be one of the most difficult challenges. This paper presents an effective HT detection method based on power side-channel features that can classify circuits under test (CUTs) into Trojan-inserted (TI) and Trojan-free (TF). It classifies the power traces based on the machine learning algorithms. The selected machine learning algorithms include supervised and unsupervised algorithms. The experimental results demonstrated on AES benchmarks show that the accuracy of TI power traces is 91.38% and 65.81% with supervised and unsupervised machine learning, respectively. Finally, it uses majority voting to perform the secondary classification on the CUTs based on the classification results of the power traces, which can mitigate the effects of process variations and noise. The experimental results show that the secondary classification can achieve 100% and 94.44% accuracy of TI circuits with supervised and unsupervised machine learning, respectively. The effect of dataset balance on machine learning performance was investigated, and a balanced dataset can improve accuracy by 13% to 30%. The experimental results on AES 8/128-bit HT demonstrate the effectiveness of the proposed method in detecting unknown Trojans.

This paper reports p-channel metal-oxide heterostructure field-effect transistors (MOSHFETs) based on p-GaN/GaN/Al_0.29Ga_0.71N heterostructures grown by metal-organic chemical vapor epitaxy (MOCVD) on Si substrates. The two-dimensional hole gas (2DHG) density in the p-GaN/GaN/Al_0.29Ga_0.71N heterostructures is 1.3×10¹³ cm^-2 and remains unchanged down to a temperature of 80 K. A reduction of the GaN channel thickness by dry etching renders the p-channel MOSHFET enhancement-mode (E-mode) with a negative threshold voltage (V_th). The E-mode p-channel MOSHFET realized by GaN (18 nm)/Al_0.29Ga_0.71N shows a threshold voltage V_th of -0.79 V, an on-current |I_ON| of 2.41 mA/mm, a low off-state drain-source current (|I_OFF|) of 2.66×10^-9 mA/mm and a low subthreshold swing (SS) of 116 mV/dec. Such ultralow |I_OFF| and SS indicates high-quality epitaxial material. The high-temperature operation capability of the p-MOSHFET is evaluated up to 200 °C.

This letter presents a 5.2-6.4GHz fractional-N phase-locked loop (PLL) with low in-band fractional spurs. The proposed probability-distribution-shaping delta-sigma modulator (PDS-DSM) reduces the in-band fractional spurs arising from loop nonlinearity by changing the probability distribution of the DSM. The enhanced PDS-DSM is realized by integrating the PDS dither with a multi-mode filter at the output stage of a conventional MASH 1-1-1 architecture. The proposed PLL was fabricated in a 65nm CMOS process. Notably, with the incorporation of second-order and third-order filtered PDS dithers in the PDS-DSM, in-band fractional spurs at 10kHz offset from 5.825GHz were reduced from -49.5dBc to -58.2dBc and -62.8dBc respectively.

This paper presents a high-linearity millimeter-wave (mmWave) Doherty power amplifier (PA) for 5G FR2 wireless communications. A precise mutual distortion cancellation (PMDC) method for parallel Doherty PA is proposed. The auxiliary path current amplitude is adjusted by the common-source common-gate (CSCG) dual adaptive bias circuit (DADB). Meanwhile, the main path current phase is tuned by the phase nonlinear compensation capacitor (PNCC). These two techniques are combined to enable precise distortion cancellation, thereby optimizing the Doherty PA’s AM-AM and AM-PM distortions. The chip is fabricated in a 40 nm CMOS process. The measurement results show that the proposed Doherty PA achieves a small-signal gain of 19.6 dB, a 3-dB bandwidth from 21 to 29 GHz, a saturated output power (P_sat) of 19.1 dBm, an output 1-dB compression point (OP_1dB) of 17.9 dBm, a peak power added efficiency (PAE_peak) of 22.7%, a power added efficiency at 6-dB power back-off (PAE_-6dB) of 15.1%, and an AM-PM distortion of 0.93° at 26 GHz. When using a 64-QAM 100 MHz OFDM modulated signal as the input, which meets the 5G NR FR2 communication protocol and has an input PAPR of 11.38 dB, the measured output EVM is -25 dB, and ACLR is -30.5 dBc. The proposed PA realizes an average output power (P_avg) of 12.6 dBm and an average power added efficiency (PAE_avg) of 11.3%.

This paper proposes a novel low-voltage and high-linearity input buffer for high-performance Analog-to-Digital Converters (ADCs). The use of current feedback and an auxiliary source follower (SF) is crucial for enhancing linearity, reducing power consumption, and minimizing the circuit area. The proposed buffer, designed in a 40-nm CMOS process, achieves a spurious-free dynamic range (SFDR) exceeding 73.6dBc at a 1GS/s sampling rate with a 3.3pF load capacitance. It occupies 0.00684mm² and consumes 43mW at 2.5V, including bias and common-mode feedback (CMFB) circuits.

We have applied the symplectic integrator (SI) scheme based on the fast Fourier transform, namely, FFT-SI, to electromagnetic field analysis for inhomogeneous and dispersive media. The auxiliary differential equation (ADE) for chromatic dispersion was formulated along with the time-dependent Maxwell equations. We examined two distinct dispersion models for ADE: one based on Sellmeier equation and the other based on the Lorenz-Drude model. Our computational results for one-dimensional problems were compared with exact solutions to examine numerical accuracy with respect to the time and space step sizes, allowing us to assess applicability of higher-order algorithms and effects of numerical dispersion errors. Extension of the present computational method for two-dimensional problems used for application development was also examined.

In this study, we proposed a low-cost and simplified method for detecting blood vessels in fat using high-frequency current during surgery. Conventional methods for detecting blood vessels are not often used in surgery because they are complex systems to detect blood vessels for surgeon. In this paper, we calculated the real and imaginary parts of impedance between two electrodes inside the presence and absence of blood vessel in the fat in kHz band. Based on the results, we could find the possibility of blood vessel detection in the fat by impedance change.

This study investigates the amplitude noise suppression of 20-Gbit/s quadrature phase-shift keyed phase-conjugated twin waves (PCTWs) by frequency non-degenerate phase-sensitive optical amplification. The amplitude fluctuations of PCTWs are converted into phase fluctuations through the optical Kerr effect in transmission optical fibers. The average phases of transmitted PCTWs are then phase-locked to the pump phase and subsequently phase-rotated by an appropriate amount. This sequence results in amplitude noise suppression through optical parametric processing when the appropriate phase rotation is applied. Numerical simulations investigate the signal-to-noise ratio (SNR) of transmitted PCTWs with optical noise simulating the noise conditions of multi-relay transmissions, in a single-span transmission model. The SNR improvement is observed irrespective of whether the optical noises between PCTWs are correlated or not.

Power obtained from ultra-small energy harvesters is often tiny and difficult to use. The circuits with high power consumption can be driven by temporarily storing that power in a capacitor for a long time and discharging it instantaneously. We propose a unique intermittent-drive CPU that can operate even if the supplied power is minimal and intermittent. Regular CPUs are reset when power is turned off, so they are reset after every intermittent drive. This is because the regular CPU assumes a stable power supply. To enable intermittent and low-power operation, the amount of power required for CPU operation consumed at one time is reduced by executing only one CPU instruction cycle at a time. After instruction cycle processing, only the information necessary to continue the operation is stored in nonvolatile memory and read back when needed in subsequent cycles. This method does not save all data simultaneously, as in the sleep operation, but saves the data by dividing it frequently. Therefore, it has the advantage of low instantaneous power consumption and does not require special devices such as nonvolatile Flip Flops. We implemented an intermittent-drive CPU using the RISC-V RV32I instruction set architecture on an FPGA and a chip fabricated in a 0.18 um standard CMOS process. The designed chip was intermittently driven successfully with 6kHz power and reset signal.

The nonlinearity of optoelectronic devices is critical in broadband systems due to harmonic and intermodulation interference. This study proposes a method to evaluate second- and third-order nonlinearities in photodetectors using optical two-tone signals with wide frequency separation. Two models address frequency-dependent effects, with corrections for accurate measurement. Experiments with amplifiers and passive components validated the approach. The method enables reliable performance evaluation of optical devices, contributing to low-distortion, high-speed optical communication systems.

Recently, research on neural light field (NLF), which applies implicit neural representation (INR) to light field (LF), has been actively conducted. NLF can reconstruct dense and realistic LF from relatively sparse and unstructured images, which alleviates the high acquisition difficulty of existing LFs. On the other hand, NLF has a slow rendering speed due to pixel-level MLP processing, making real-time rendering challenging. To address real-time rendering of NLF, this paper considers the application of an explicit voxel grid (VG) data structure, which is used to improve the rendering speed of INR. In particular, the performance is compared based on the dimensions of VG. Experimental results show that the dimensions of VG involve a trade-off between rendering quality, memory usage, and training speed. The analysis presented in this paper is expected to help select the appropriate dimensions of VG according to the specific application scenario.

In this study, a generalized BLT equation based on EMT is proposed to predict the SE of the rectangular enclosure with complex apertures. Aperture structures are decomposed into rectangular units, with equivalent impedances computed using Robinson’s coplanar stripline model or Nie’s capacitive-inductive diaphragm model. The Robinson model considers the influence of eccentric apertures by introducing the aperture position factor and takes into account the high-order modal effect and the SE prediction from any observation point. The results show that the Robinson model performs better than the Nie model in the high-order modes, both of which are effective under the main mode conditions, and the Nie model is more adaptable to the aspect ratio of the aperture. The effectiveness of this method in SE prediction of the rectangular enclosure with complex apertures is verified by comparison with CST Studio Suite.

Low-offset operational amplifiers are widely employed in readout circuits. Conventional calibration techniques such as chopper or fuse trimming face the inherent contradiction between repetitive calibration and small area and power consumption. Memristors offer a promising alternative with their unique characteristics of continuously variable resistance, repeatable programmability, and compact size. This paper proposes a memristor-based multiple-time adaptive trimming circuit for amplifier offset. A folded cascode two-stage operational amplifier was fabricated using the 180nm CMOS process and trimmed by the proposed technique. Chip testing demonstrates that it reduces amplifier offset voltage to below 57.8μV level while occupying only 1829µm² of circuit area, providing a new low-cost feasible approach for repeatable offset compensation.

In this letter, a rasorber with an ultra-wide electromagnetic (EM) wave absorption bandwidth is proposed, which is composed of multiple layers of indium tin oxide (ITO) resistive films with different structures and a metal ground. The rasorber has an absorption rate of over 90% at 1 GHz - 21.2 GHz under different polarized waves vertically incident, with a relative bandwidth of 182 %. When EM waves are obliquely incident, it can maintain an absorption rate of over 80% in the range of 45 °under TE and TM polarization, with angular incidence stability. An improved genetic algorithm was used to optimize the rasorber performance during the design process. An array prototype of the proposed structure is fabricated for testing and the experimental results match the simulation. The proposed rasorber belongs to EM metamaterials, with a cell period size of 0.167λ_L and a thickness of 0.1λ_L, offering advantages in miniaturization and low-profile.

A high-speed and high-slew-rate operational amplifier (OPA) is presented in this paper. The gain boosting circuit is embedded in the circuit in order to improve the open-loop DC gain, which significantly improves the overall gain without adding additional stages and ensures high performance under low supply voltage conditions. In order to meet the demand for fast response in high-speed applications, the slew rate enhancement circuits are proposed to reduce the large signal build-up time of this OPA. Meanwhile, the operational amplifier employs the Ahuja compensation method to improve the phase margin (PM) of the circuit and is able to achieve a higher unit gain bandwidth with a smaller compensation capacitance. The proposed operational amplifier is designed based on TSMC 0.18µm CMOS process with a chip area of 0.468mm². Post-simulation results show that the op-amp has an open-loop gain of 111dB, a unit gain bandwidth of 240 MHz, and a phase margin of 62°. The measured quiescent current is 3.1mA under the 5V supply voltage, and the slew rates are 403V/µs and 386V/µs with the help of the slew rate enhancement circuits.

This paper presents a low power LDO circuit that can operate with a maximum input voltage of 30V without the need for a bandgap reference. The LDO leverages a combination of an error amplifier and a biasing circuit, allowing for the generation of a stable output voltage solely from the bias current, thereby eliminating the inherent challenges associated with high-voltage references, such as poor PSRR and complex startup mechanisms. The proposed design effectively reduces the circuit's footprint and power consumption. The implementation is based on a 0.18µm process. The input voltage range for the LDO is 3.5-30V, a maximum load current of 1mA, a dropout voltage of 1.25V, a power supply rejection ratio (PSRR) of 111dB, a line regulation of 4.5µV/V, a load regulation of 6.7μV/mA, and a power consumption of 1.5µA.

Nowadays, Frequency-Modulated Continuous Wave (FMCW) radar systems are widely used. These radar systems usually suffer from undesired patterns include the interference from transmitter or LO, multiple reflections of static objects in the environment. Traditional baseband processing uses high-pass filters (HPF) to suppress these interferences; however, HPFs have both slow settling due to low cut-off frequency, and attenuation to real objects reflections at near frequency band. Some studies have tried to cancel the interference actively, however additional cancel errors are induced. In this paper, a novel active cancel methodology is proposed with pattern cancel DAC and remove the cancel error with feedforward compensation. It is verified on silicon to be effective to mitigate the interference and enhance the linearity of the FMCW baseband greatly.

This study proposes a novel technique called the guided spontaneous emission circuit (GSEC) technique that can largely enhance the optical power resolution (OPR) of optical power variation measurement systems. The improvement factor (IF) in the OPR achieved by the GSEC technique is determined by the slope of the nonlinear optical input-output curve in dBm of the GSEC. Through experimental analyses, we clarified the characteristics of the IF and successfully optimized it by implementing a two-stage GSEC with two erbium-doped fibers (EDFs) and two optical filters. By optimizing the configuration of the two-stage GSEC, we achieved an optimized IF of approximately 30.6.

This paper proposes a 5-transistor (5-T) voltage reference (VR) with enhanced self regulation for low-voltage and low-power applications. In the proposed circuit, the gate feedback with the source degeneration is applied to a transistor to form the enhanced self regulation to reduce the impact of the supply voltage (V_DD) on the reference voltage (V_REF). Moreover, a stacked gate-source connected transistor further increases the impedance from the V_DD to ground. In this way, both line sensitivity (LS) and power supply rejection ratio (PSRR) can be improved without any additional current overhead. The proposed VR is fabricated in a 0.18 μm CMOS process, while 10 samples have been measured. It can provide a V_REF of 387.1 mV and consume a power consumption of 50.4 pW at 27℃. The results show that the average LS reaches 0.014 %/V when the V_DD varies from 0.6 V to 5 V. Additionally, the PSRR is -73.5 dB and -49.4 dB at 10 Hz and 100 Hz respectively. The average temperature coefficient (TC) is 80.8 ppm/℃ without any trimming from 0℃ to 100℃. The total area of the proposed VR is only 0.0038 mm².

To meet the demands of 5G base stations in large PAPR signal environments, this paper presents the design of a 550W improved three-stage Doherty power amplifier with a 12 dB back-off range. GaN HEMT devices with gate widths of 18 mm, 27 mm, and 27 mm are selected for internal matching design to ensure ultra-high output power. The paper analyzes the active load modulation mechanism under an asymmetric architecture and proposes an impedance matching design method suitable for this configuration. Test results in the 2.5-2.7 GHz show that the linear region gain is between 10.5 and 13.4 dB, the saturated output power ranges from 57.2 to 57.6 dBm, and the saturated drain efficiency is between 69% and 73%. At a 12 dB power back-off, the drain efficiency is between 55% and 58%. When the power back-off is 6 dB, the drain efficiency ranges from 62.2% to 65.1%. After incorporating Digital Pre-Distortion (DPD) technology, the ACPR test result is -55.9 dBc. These results address the issues of insufficient back-off range and linearity degradation due to saturation, which are common in traditional three-way and three-stage Doherty power amplifiers.

In current multi-core systems, the MCU typically employs a full instruction set, but only a limited subset of instructions is actually utilized, leading to wasted area and power consumption. This study presents the design of a RISC-V-based coprocessor, MiniRV, aimed at improving resource utilization in multi-chiplet systems, reducing both area and power consumption while maintaining task execution efficiency. The coprocessor features a three-stage pipeline structure, enabling simplified design and minimal area occupation. A dedicated compiler was also developed to support its instruction set. The validation results show that, compared to PicoRV32, MiniRV reduces area by 43.14%, power consumption by 38.86%, while the code execution efficiency remains unchanged.

This study presents a W-band antenna integration module using High-Density Interconnect (HDI) technology for radar applications. The module integrates 64 transmit/receive (TRX) channels, each with a 2×2 sub-array, forming a 16×16 antenna array. To address warpage and manufacturing constraints caused by asymmetric copper coverage in HDI substrates, we introduce non-resonant patches and cavity structures, enhancing copper uniformity and gain performance. Broadband impedance matching techniques mitigate vertical impedance discontinuities. A single TRX channel demonstrates a 23.35% impedance bandwidth (87-110 GHz) and a peak gain of 13.74 dBi. The full module's simulated peak gain reaches 26.83 dBi at 97 GHz, confirming the viability of HDI technology for W-band antenna integration.

The nerve electrical stimulation is an effective way to treat neuropathic diseases. Normally, the mice are the subjects for neural stimulation. In order to solve the problem of decreasing transmission efficiency and frequency mismatch of wireless power supply during the experiment caused by the movement of the mice, a squirrel cage system based on wireless power transfer combined with temporally interference is proposed in this paper. The low frequency envelope current superimposed by high frequency power supply with small frequency difference is used for nerve electrical stimulation. It is proved by simulation and experiment that the proposed squirrel cage system can generate stable magnetic field in more than 80% area when the operating frequency is 300 kHz.

Due to the dynamic changes in vibration, energy harvesting using Piezoelectric Transducers (PZT) faces challenges with limited harvesting power. Hence, this paper presents a hybrid rectifier with dual-modes Synchronous Electric Charge Extraction (SECE) method for harvesting piezoelectric energy, aiming to achieve a higher output power. In situations where electric energy is insufficient, the rectifier operates in the passive SECE mode, enabling energy harvesting without a power supply and helping to self-start faster. When there is sufficient electric energy, it adaptively switches to the active SECE mode to enhance harvesting efficiency. Measurements indicate that the maximum power harvested in the passive SECE modes can be up to 2 times that achieved with the traditional full-bridge rectifier, and the peak conversion efficiency reaches 83% in the active SECE mode.

This paper proposes an analog front-end circuit applicable to single-lead ECG signal acquisition based on a 0.18um process. The circuit employs an AC capacitive coupling instrument amplifier (ACIA) with a DC servo loop, significantly improving input impedance. Simulation results indicate an input reference noise of 8.538 uVrms, an ECG signal voltage amplification factor of 30 V/V to 240 V/V, and an input impedance of 4.59 GΩ @15 Hz. The circuit also features low input noise and a high common-mode rejection ratio of 114 dB.

Based on the study of the influence of the air gap length on the core characteristics, a method to determine the optimal air gap length of the core is proposed for energy harvesting of transmission lines. The equivalent model of the core is established, and the relationship between the optimal air gap length and the saturation primary current is derived. The simulation and experimental results show that when the air gap does not exceed 5% of the length of the magnetic circuit, the saturation characteristic model established in this paper can accurately calculate the optimal primary current with a calculation error of less than 5%. The air gap length corresponding to the optimal primary current is the optimal air gap length, and at the optimal air gap length, the core output efficiency is close to maximum, which has specific engineering utility value.

In pursuit of an efficient and precise method for measuring the Leaf Area Index (LAI), this paper designs and implements a portable LAI measurement instrument based on hemispherical photography, designated as LAI-HP. Constructed upon an embedded platform, this device integrates advanced functionalities of image acquisition, processing, and storage in a single compact unit. Not only does it simplify operational procedures, enabling users to readily master the measurement technique, but it also ensures high accuracy by providing exact analysis of hemispherical canopy images, thereby rapidly and accurately extracting the leaf area index. Comparative experiments reveal a highly significant correlation between the measurement results of LAI-HP and those obtained from the LAI-2200C (R =0.889, RMSE =0.441), demonstrating its capability to meet the requirements for LAI measurements in major ecosystems such as farmlands and forests.

True random number generator (TRNG) is an essential part of cryptographic systems. In this paper, a high bit rate and self-stable probability TRNG based on spin-orbit torque magnetic tunnel junction (SOT-MTJ) is proposed. The TRNG reaches 16.7 Mb/s bit rate and 93.62 pJ/bit energy consumption for a single cell. In addition, the TRNG achieves a stable probability of random numbers regardless of the voltage and device to device variation. The random bits have passed the National Institute of Standards and Technology statistical test suite. Our results provide a candidate of high bit rate TRNG for IoT security applications.

As advancements in power integrated circuit design and semiconductor technology continue, motor drivers are evolving toward smart power integrated circuit (SPIC). This paper presents the design of a high-voltage, two-phase stepper motor driver chip based on a 0.18 μm BCD process. The driver integrates several key modules, including a low-voltage power module, current sensing module, charge pump module, driver circuit module, and protection module. To improve system stability and precision, two sets of cascode current mirrors are employed to sample the H-bridge current. Test results demonstrate that the chip can reliably operate within a supply voltage range of 8 V to 40 V, achieving a maximum current output of 2 A and a continuous drive current of up to 1.6 A. Furthermore, the chip exhibits stable current steps with each stepping pulse.

This brief presents a power-efficient PAM-4 transmitter. The proposed hybrid voltage-mode current-mode (VM-CM) driver with push-pull current-mode equalization reduces the power consumption. The date-dependent jitter (DDJ) suppressed C²MOS MUX is devised to reduce the output jitter and power of prior widely used C²MOS MUX. The phase aligner is utilized to provide sufficient time margin for the high-speed 4-1 MUX, thus no power-hungry high-speed latches along with its clock buffer are required for retiming. Fabricated in 40-nm CMOS, our prototype can operate at 56 Gb/s data rate with 0.7 pJ/bit energy efficiency and 6.1 dB channel loss at Nyquist frequency of 14 GHz, namely achieving a figure-of-merit (FOM) of 0.11 pJ/bit/dB.

This letter presents a high-linearity input buffer for RF sampling ADC. A common-source operational amplifier is added as a bootstrap circuit to mitigate the influence of channel-length modulation and current extracted by sampling circuits. A cross-coupled substrate technique is introduced to enhance the output impedance of tail current sources, thereby further improving linearity. The proposed input buffer is designed using a 40-nm CMOS process, consuming 60-mW under a 2.5-V supply, which can be applied in a 1.5-GS/s 14-bit pipelined ADC. Simulation results demonstrate that the input buffer achieves an SFDR/SNDR of 80.3/69.2 dB with a 1283-MHz input at 1.5-GS/s.

A novel broadband circularly polarized (CP) all-dielectric transmitarray antenna (TA) in millimeter-wave (mmWave) band is designed using “Hamburger” shaped unit-cell in this paper. A circular contour TA is constructed by optimizing the transmission phase of each unit-cell to realize a specific phase distribution on the TA surface. The proposed TA is fabricated using 3-D printing technology. It achieves a peak gain of 27.8 dBi with an aperture efficiency of 46.7% at 39 GHz, a 1-dB gain bandwidth of 22.1% and a 3-dB ARBW of 21%, respectively.

This paper reports a waveguide for terahertz electromagnetic wave transmission, featuring a complex multilayer stepped bend waveguide. The waveguide was fabricated on a silicon wafer using deep reactive ion etching, which had better mechanical performance compared to Silicon-On-Insulator based etching. After etching, the wafer underwent gold plating, low-temperature bonding, and dicing to produce the silicon waveguide, overcoming the integration challenges and slow processing of metal based waveguides. The experimental work focuses on investigating the key fabrication parameters that influence the waveguide’s transmission performance, as well as optimizing the Bosch process for etching the multi-layer stepped structure. Finally, an analysis was conducted on the differences between the measurement and simulation results. Results showed that the insertion loss of the waveguide was about 0.5 dB within the 300–530 GHz, achieving low-loss terahertz electromagnetic wave transmission.

In this paper, a smart system monitoring sensor based on a 12-bit SAR ADC with hybrid DAC is presented, and fabricated in a standard 55-nm CMOS process. By utilizing a MUX to switch the input channel, monitoring of the temperature and voltage at critical points is achieved. Additionally, a double conversion method is also proposed for circumventing the current mismatches of the two BJT temperature sensing elements, thereby lower the circuit complexity. For temperature sensing, the sensor shows a measured inaccuracy of ±1.5℃ from -55℃ to 125℃ with an resolution of 0.86℃. For voltage sensing, the ADC shows a measured DNL and INL of +0.43/-0.47LSB and +1.4/-1.1LSB, respectively. Thanks to the proposed technique, the sensor consumes low power of 182μW under a 1.8/1.2V supply at a conversion speed of 156kS/s, and occupies an area of 0.074mm².

This study presents the relation between transmission cross section (TCS) and directivity (D) of a narrow slot in an infinitesimally thin and perfectly conducting screen. Although TCS is recognized to increase proportionally with increasing D according to 2Dλ²/4π, this paper shows that TCS is not proportional to D in the imperfect transmission. The resonant transmission (RT) factor defined by D, 0≦K_RT≦1, was used to explain the transmission quality related to TCS and D. The perfect-RT (K_RT=1) occurs at the first resonance slot length as a perfect parallel resonance and leads to perfect transmission. In this perfect-RT, TCS is equal to . However, the imperfect-RT (K_RT＜1) occurs at the second resonance slot length and thereafter as an imperfect resonance and leads to imperfect transmission. In this case, TCSs are not equal to 2Dλ²/4π due to the imperfect resonance caused by the stored reactive power.

To solve the problem pertaining to voltage overshoot arising from frequent switching in CAN transceiver interface circuits, and to mitigate electromagnetic interference while protecting the circuit, this paper proposes a new low-voltage overshooting CAN transceiver interface circuit based on a 0.18μm BCD. The high-voltage switching transistor is controlled by comparing the bus voltage with a reference voltage to achieve real-time monitoring and protection of the bus voltage. The simulation results show that the interface circuit has excellent power consumption, anti-interference ability, and signal integrity, with a power consumption of 24.2μA and bus voltage symmetry of 0.934-1.052 under the passive state of the bus.

Mel-frequency cepstral coefficients (MFCC), an FFT-based speech feature extraction (FEx) algorithm, is a significant power consumer in low-power keyword spotting (KWS) chips. This work presents a KWS chip with an energy-efficient FEx, with an expanded-3bit-twiddle FFT (E3bT-FFT) algorithm which reduces power of FFT by 5.7x. Meanwhile, a multiplier-free MFCC (MF-MFCC) is proposed, effectively eliminating power-hungry multipliers and reducing the MFCC computational load by 7.3x. Fabricated in a 65-nm CMOS process, the chip occupies 0.17 mm² and consumes 2.3 µW, with the computation unit in FEx consuming just 76 nW, and achieves 94.9% accuracy on a 1-Word KWS with Google Speech Commands dataset (GSCD).

In this paper, an Efficiency Optimization Strategy (EOS) is proposed to address the issue of low efficiency in the Dual Active Bridge (DAB) DC-DC converter across certain power ranges under wide voltage conditions, with the aim of further enhancing the converter's efficiency over a broad operating range. First, in the low power range, a phase-shift control strategy is introduced, which enables wide-range Zero Voltage Switching (ZVS) and near-optimal inductor current RMS values. Through this strategy, ZVS is ensured for all switches under light load conditions, while under medium load conditions, ZVS is lost for only two switches. Subsequently, in the high power range, the optimization target is smoothly transitioned to the optimal RMS current value by utilizing the natural ZVS characteristics of the DAB converter. The operating range of the EOS is effectively extended, further reducing current stress and RMS current values, thereby achieving global efficiency optimization of the DAB converter. Finally, an experimental platform is constructed for verification, and the correctness and effectiveness of the theoretical analysis are confirmed by the experimental results.

While CNT FETs have been demonstrated to exhibit excellent resistance to irradiation, the radiation effects in complex environments remain relatively understudied. This paper investigates the synergistic effect of CNT FETs under the combined action of ionization and displacement damage using proton irradiation. It was observed that the V_th degradation (0.06 V) induced by 40 MeV protons was twice that (0.03 V) induced by 70 MeV protons with the same ionization dose. The numerical simulations indicated that the 40 MeV proton irradiation results in the formation of displacement defects in closer proximity to the semiconductor channel. This increased the hole capture rate, leading to a higher concentration of fixed charge in the SiO₂ layer and a larger threshold voltage shift.