A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

Released on J-STAGE: May 25, 2023 | Volume 20 Issue 10 Pages 20230050

Wenya Chen, Qingsong Cai, Zhong Yang, Shushan Qiao

Views: 541

Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide

Released on J-STAGE: November 16, 2022 | Article ID 19.20220465

Jongwoo Kim, Hyungjun Jo, Yonggyu Cho, Hyunyoung Shim, Jaesung Sim, Hyungcheol Shin

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A compact model for dual-gate GaAs PHEMT and application for power amplifier design

Released on J-STAGE: October 25, 2021 | Volume 18 Issue 20 Pages 20210268

Zhihao Lv, Zhiwei Xu, Chunyi Song

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March-based SRAM diagnostic algorithm for distinguishing Stuck-At and transition faults

Released on J-STAGE: August 10, 2009 | Volume 6 Issue 15 Pages 1091-1097

M. I. Masnita, W. H. W. Zuha, R. M. Sidek, A. H. Izhal

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A 64-Gb/s PAM-4 Digital-Assisted Micro-ring Modulation Driver with Nonlinearity Compensation in 28nm CMOS

Released on J-STAGE: May 08, 2026 | Article ID 23.20260157

Siyuan Ma, Shihuan Ran, Qianli Ma, Yihan Chen, Bolun Cui, Guike Li, Shuangming Yu, Zhao Zhang, Jian Liu, Linjie Zhou, Nan Qi, Liyuan Liu

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