Article ID: 13.20161116
In this paper, a novel built-in jitter measurement circuit (BIJM) for Phase-Locked Loops (PLL) based on a variable vernier delay line (VVDL) is proposed. Resolutions of the two-level VDLs can be designed flexibly and their lengths optimally according to the signal under test (SUT). A digitally controlled delay element (DCDE) using varactors acts as the basic delay element in VVDL. Instead of counters, thermometer-to-binary encoders are adopted in the design. An improved phase detector (PD) is also introduced. The circuit has been designed using an all-digital design methodology and verified with the TSMC 130nm CMOS process. 800MHz clock frequency is chosen, and the circuit occupies a total silicon area of 0.043mm2, which is reduced by 60% compared to the traditional VDL. Simulation results indicate coarse timing resolution of 15.4ps and fine resolution of 2.1ps, and measurement error is within 2.11%.
