Design of the convolution layer using HDL and evaluation of latency using a camera signal

Abstract

Deep learning is used in various applications and fields and is expected to be used in embedded systems such as IoT devices. However, it requires large computational costs, high power consumption, and using a GPU generally, so, it is a hard point to implement on tiny embedded devices. Also, in recent years, FPGAs have been applied to image processing technology fields such as defect inspection of automobiles, security systems, and industrial products. Hardware acceleration is one of the techniques to improve processing speed and it is often used in the field of image processing. In our work, the hardware acceleration for the convolutional neural network was designed compared to software processing. These hardware-based modules were implemented on FPGA. In this paper, we show the detail of the architecture and the comparison result of processing time with CPU.