抄録
Two novel placement methods for E-beam testing pads are proposed to improve the placement ratio in multilevel-wiring LSIs. In the first method, which is for the case where upper-level wires obstruct the placement of testing pads, stepped vias are introduced in testing pads so that testing pads can go around the upper-level wires outside the cells. This method has been applied to layout design data of gate-array LSIs containing from 20 to 390-k gates. Results of evaluation confirms that observability reaches more than 99.6%. In the second method, which is for the case where all the top-level wires are used for power supply, an opening is made in the power-supply wires so that a testing-pad to be placed may not short-circuit the wires. As a result of evaluation using actual design layout, resistive increase due to the openings in the wires was found to be so small that the method can practically be used for test pad placement. These proposed methods will be essential for fault analysis of multilevel-wiring LSIs.
