Current 4H-SiC wafers contain certain amount of dislocations, stacking faults and other lattice-defects. These defect structures evolve during various processes for power device fabrication. It is very important to examine evolutions of dislocation structures during power device processes, as well as the effect of dislocations on performances of fabricated power devices. Since lattice defects can be observed at only subsurface regions selectively by Berg-Barrett X-ray topography, we have applied this useful observation technique to 4H-SiC technology to solve various technological issues. Appearances of scratch-like surface morphology after epi-film growth on very flat substrate surface by CMP were examined by this technique, and the mechanism was discussed. Analysis of dislocation structure evolutions during epi-film growth, also basal-plane dislocation glide by recombination of electrons and holes were discussed. Effects of threading screw dislocations on reliability of MOS structures, and on current leakage in pn-junction under reversed bias condition were investigated and discussed. Various important suggestions for 4H-SiC industries were obtained.
J-STAGEがリニューアルされました！ https://www.jstage.jst.go.jp/browse/-char/ja/
