抄録
An algorithm for generating a multi-level NAND logic circuit is proposed. In the algorithm, (a) to cover true (1) cell, permissible cubes described by the product of the affirmative literals are generated; and (b) if false (0) cell is found in the generated cube, new permissible cubes excluding the false cell are added. Procedures (a) and (b) are repeated until no true cell exists together with false cell in the permissible cube. The finally obtained cubes are converted into a NAND gate circuit. The circuit generation is carried out only by the mouse operations and the circuit can easily be displayed on a screen.
