Dependable Design of Multi-processor System for Advanced Train Control System CARAT

Abstract

In this paper the architecture of a dependable multi-processor system for an advanced train control system is discussed. The multi-processor system is composed of a fail-safe computer and some peripheral interface computers. Dependability of the system calls for complete safety as well as high system reliability. It is for this reason that we developed a bus-level synchronous fail-safe computer and 32 bit type LSI comparator which is used as a self-checking element for the fail-safe computer. For the purpose of system reliability, a duplex architecture of multi-processors which consists of two connected independent system buses, i.e. VME-buses, with dual-port memory is developed. This method, called a mirror-memory scheme, assures continuous processing during exchanging interval.