Recent Developments in Floorplan Representations

抄録

A floorplan is a partition (dissection) of a rectangle into smaller rectangles by horizontal and vertical line segments such that no four rectangles meet at the same point. Floorplans are used to design the layout of very-large-scale integration (VLSI) circuits. Since modern VLSI circuits are extremely large, it is necessary to design compact floorplans (VLSI layouts). In 2004, Feng et al. surveyed ways of representing floorplans. However, over the past decade, various new methods have been developed, and in this paper, we survey these recent developments in floorplan representations.