Information and Media Technologies
Online ISSN : 1881-0896
ISSN-L : 1881-0896
Hardware and Devices
Checker Generation of Assertions with Local Variables for Model Checking
Sho TakeuchiKiyoharu HamaguchiToshinobu Kashiwabara
著者情報
ジャーナル フリー

2009 年 4 巻 2 号 p. 227-239

詳細
抄録

To perform functional formal verification, model checking for assertions has attracted attentions. In SystemVerilog, assertions are allowed to include “local variables”, which are used to store and refer to data values locally within assertions. For the purpose of model checking, a finite automaton called “checker” is generated. In the previous approach for checker generation by Long and Seawright, the checker introduces new state variables corresponding to a local variable. The number of the introduced state variables for each local variable, is linear to the size of a given assertion. In this paper, we show an algorithm for checker generation in order to reduce the number of the introduced state variables. In particular, our algorithm requires only one such variable for each local variable. We also show experimental results on bounded model checking for our algorithm compared with the previous work by Long and Seawright.

著者関連情報
© 2009 by Information Processing Society of Japan
前の記事 次の記事
feedback
Top