Design of Synthesizable Digital Phase Locked Loops

抄録

Phase-locked loops (PLLs) are crucial building blocks in almost everry electronic device. With the continuous scaling down of CMOS process, conventional custom-designed PLLs based on analog circuits suffers from the large area, degraded performance, and long design time. This paper introduces fully synthesizable PLLs based on purely digital standard cells. The fully synthesizable PLLs are compact and can be designed using commercial digital synthesis tools. Design time for synthesizable PLLs is much shorter than conventional analog PLLs, especially given a new technology. Injection-locked architecture is adopted in the synthesizable PLLs to improve the PLL performance. Synthesis method to automatically design the synthesizable PLLs is described in this paper. Furthermore, building block design is introduced. Finally, design examples of injection-locked PLLs are introduced, and their performance is compared with that of custom-designed PLLs.