n-チャネル低温poly-Si TFTの電界, キャリヤ分布の2次元シミュレーション

抄録

To analyze hot-carrier degradation, we developed a two-dimensional (2-D) physical model of n-channel poly-Si LDD TFT. The model is based on a 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si from a 2-D process simulator. We have shown that, in current saturation bias, the maximum 2-D lateral electric field is in the deep LDD region under the gate edge, and the current flows in the deep channel region near the LDD junction. These results suppose that the drain avalanche hot-carrier (DAHC) degradation first occurs due to the state generation at both the gate oxide/poly-Si interface and the grain boundaries in the deep channel region near the channel/LDD junction.