抄録
A high speed 2-D motion vector detection on CMOS sensor focal plane is proposed. Edge detection circuit composed of two crossed differential OTAs with time-multiplexed sampling is adopted for getting horizontal and vertical edges. 4-bits short-time digital memory is designed by transmission gate array, which can keep edge information by a smaller layout area. High speed block matching is designed by a Local Parallel and Global Collumn Parallel (LPGCP) processing architecture, which makes use of the parallel nature of images. The size of block for matching is reduced to 2×2 pixels and a search area of (±1, +1) pixels at a high frame rate, such as 1000 frames/sec. Experimental results of pixel circuit with PD, edge detection and memory are given.
