ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
25.55
Session ID : IPU2001-72
Conference information
Image Enhancement in a Highly Parallel Architecture
Namiko IKEDAMamoru NAKANISHIKoji FUJIITakuya ADACHITakahiro HATANOSatoshi SHIGEMATSUHakaru KYURAGI
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CONFERENCE PROCEEDINGS FREE ACCESS

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Abstract
An image enhancement algorithm is described that can be mapped with high resolution onto a compact two-dimensional array of processing elements. To prevent the structure of the object being observed from being destroyed locally, the best filter is selected and applied locally on the basis of whether or not the structure of the object is easily destroyed. Experiments showed that the proposed image enhancement has almost the same accuracy as the general method, which needs an additional processing chip. It is thus suitable for application to the compact architecture of a single-chip fingerprint-identification and CMOS vision chip that integrates a sensing circuit and a two-dimensional processing circuit.
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© 2001 The Institute of Image Information and Television Engineers
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