Abstract
In this report, we propose an analog-digital hybrid LSI that emulates multiple synchronized phase-locked loops (PLLs) for a clock distribution network. The distributed PLL is emulated by a 2-D oscillator network consisting of multiple oscillator circuits that mimic elemental circuits of PLLs (phase detectors, loop filters, and VCOs). Numerical simulation of large-scale distributed PLL is very difficult because the load of simulations increases exponentially as the scale of the PLL network increases, while the emulation load is independent of the scale of the PLL network in the proposed circuit because the load is distributed into each oscillator. We here introduce the distributed PLL, its simplified model and analog-digital hybrid circuits of the proposed model, and show performances (synchronization and mode lock) of the circuit by using HSPICE. Large-scale integration of the proposed circuit may facilitate the design of GHz clock distribution networks.
