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Displaying 1-18 of 18 articles from this issue
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Article type: Cover
Pages Cover1-
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (12K) -
Article type: Index
Pages Toc1-
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (70K) -
Hidekuni Takao, Rikiya Asaoka, Yoshiaki Ito, Kazuaki Sawada, Syoji Kaw ...Article type: Article
Session ID: IPU200255
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn this paper, a fabrication technology of JFET integration in standard CMOS is presented. JFET is used in CMOS (operational) amplifiers for realization of very low-noise sensor interface circuits. JFET devices are formed with "well" structures in standard CMOS circuits. In a p-well region, n-type channel is formed by deep P ion-implantation with energy of 150 keV to connect n+ source and drain region already formed. After that, p-type top gate is formed by B ion-implantation with energy of 30 keV. Fabricated JFET devices showed larger transconductance as compared to MOSFET devices formed on the same die. Noise power-spectrum of fabricated JFET was also evaluated, and very low-level noise amplitude was observed.View full abstractDownload PDF (1025K) -
Takashi YAMADA, Yoshimasa HONMA, Tetsuya ASAI, Yoshihito AMEMIYAArticle type: Article
Session ID: IPU200256
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn this report, we propose an analog-digital hybrid LSI that emulates multiple synchronized phase-locked loops (PLLs) for a clock distribution network. The distributed PLL is emulated by a 2-D oscillator network consisting of multiple oscillator circuits that mimic elemental circuits of PLLs (phase detectors, loop filters, and VCOs). Numerical simulation of large-scale distributed PLL is very difficult because the load of simulations increases exponentially as the scale of the PLL network increases, while the emulation load is independent of the scale of the PLL network in the proposed circuit because the load is distributed into each oscillator. We here introduce the distributed PLL, its simplified model and analog-digital hybrid circuits of the proposed model, and show performances (synchronization and mode lock) of the circuit by using HSPICE. Large-scale integration of the proposed circuit may facilitate the design of GHz clock distribution networks.View full abstractDownload PDF (660K) -
Masanori FURUTA, Shoji KAWAHITO, Daisuke MIYAZAKIArticle type: Article
Session ID: IPU200257
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSAn estimation method, in which digital correction coefficients due to capacitor mismatch in pipelined ADC are directly measured by the error coefficients using the ADC INL plot, is described. The proposed technique can be applied for various types of pipelined ADC architectures. Test results using an implemented 10-bit pipelined ADC show that the ADC achieves a maximum signal-to-noise-and-distortion ratio of 56.5dB, a maximum integral non-linearity of 0.3 LSB, and a maximum differential non-linearity of 0.3 LSB using the digital calibration.View full abstractDownload PDF (658K) -
Minoru FUJISHIMA, Koichi ISHIDAArticle type: Article
Session ID: IPU200258
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA novel analog to digital converter consisting of sigma-delta modulator and chopper-stabilization circuit, which is suitable for converting a small signal such as electrocardiogram since the scheme inherently suppress low-frequency noise such as thermal drift, is presented. This scheme inherently suppress DC offset and thermal drift by chopping the input signal at a half of the sampling frequency and shaping the quantization noise to minimize at the Nyquist frequency. The scheme, namely highpass sigma-delta modulation, is numerically analyzed using the MATLAB and experimentally verified using a field programmable analog array chip.View full abstractDownload PDF (618K) -
Takeshi YOSHIDA, Takayuki MASHIMO, Miho AKAGI, Atsushi IWATA, Masayuki ...Article type: Article
Session ID: IPU200259
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSSmall neural signal sensing systems with multi-input-channels are desired to observe a relationship between body actions of small animals and neural signals accurately in physiology and biology. In this work, we designed an analog multiplexer, chopper-stabilized amplifier and an analog-to-digital converter using an analog-digital mixed CMOS-LSI technology. The designed sensing LSI enables to measure ultimately small neural signals by a low-noise amplifier. It is possible to efficiently measure a neural signal by selecting the best channel that detects typical signal waveform.View full abstractDownload PDF (687K) -
Satoshi SHIGEMATSU, Hiroki MORIMURA, Katsuyuki MACHIDAArticle type: Article
Session ID: IPU200260
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA new fingerprint sensing and digital-conversion scheme is proposed. In this scheme, transforming the sensed signal to a time axis widens the dynamic range of the signal, and the transformed signal is converted to the digital signal with variable range and offset. These features make it possible to sense various fingerprints clearly. We also propose a flow that adjusts the quality of the fingerprint image adaptively. The effectiveness of the scheme on sensing fingerprints clearly was confirmed by a test chip fabricated using 0.5-μm CMOS/sensor process.View full abstractDownload PDF (758K) -
Shoji KAWAHITOArticle type: Article
Session ID: IPU200261
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSRecent developments in CMOS image sensors are reviewed. High-speed camera, wide-dynamic-range camera, and range imaging are typical examples of recent success of CMOS image sensors. The fastest CMOS image with 1000 M pixels reaches 1000 frames/s. Many techniques for achieving wide dynamic range have been proposed. CMOS image sensors employing wide dynamic range pixels with logarithmic response are applied for imaging of arc-welding process. CMOS sensors for real-time range imaging based on light stripe scanning, TOP (time of flight), and stereoscopic measurement methods are developed. The image quality of CMOS image sensor is being improved by the process technology and signal processing techniques. This paper gives also prospects of CMOS image sensors.View full abstractDownload PDF (882K) -
Izumi KOBAYASHI, Koichi MIZOBUCHI, Shunji KASHIMA, Takahiro NISHIWAKI, ...Article type: Article
Session ID: IPU200262
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIMPACTRON is the novel solid state image intensifier based on Impact Ionization to multiply photo-generated charge directly before its conversion into voltage. This charge carrier multiplication provides a gain in charge domain, thus avoiding the limiting effects of the amplifier noise floor. IMPACTRON realizes the low light level sensing in real time, with enough S/N ratio, without reducing the readout speed. This paper describes a brief of the concept, the outline of the typical sensor design "TC253SPD" with some important detail related to the measurement and the analysis of the noise component. The performance of IMPACTRON is also compared in terms of the visibility of the night scene.View full abstractDownload PDF (913K) -
Toshifumi IMAMURA, Yoshiko YAMAMOTO, Atsushi IWATA, Hideaki ISHIZU, Ta ...Article type: Article
Session ID: IPU200263
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSApplication of a conventional image sensor to ITS, security monitoring, and so on is hampered by its small dynamic range, 60-70dB, due to a single fixed exposure time for all pixels. To accommodate large contrast of brightness existed in an image for such applications, sensors with over 100 dB dynamic range are necessary. In this paper we propose a technique that extends dynamic range of CMOS image sensors by adjusting both the exposure time and readout circuit gain on a pixel-by-pixel basis, and expressing the input illumination in floating-point representation. From the HSPICE simulation we obtained 90 dB dynamic range and 9-bit linearity for 6-step exposure time and 3-step readout circuit gain. The result suggests that further splitting the exposure time into 8 steps we are able to achieve dynamic range beyond 100 dB.View full abstractDownload PDF (842K) -
Hiroaki ISHIWATA, Nagataka TANAKA, Tetsuya YAMAGUCHI, Hisanori IHARAArticle type: Article
Session ID: IPU200264
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA CMOS image sensor with a high sensitivity and buried photodiode has been developed. The sensor has sensitivity comparable to that of CCD imagers.View full abstractDownload PDF (687K) -
Jun OHTA, Keiichi ISAKARI, Keiichiro KAGAWA, Takashi TOKUDA, Masahiro ...Article type: Article
Session ID: IPU200265
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe have fabricated and demonstrated fundamental characteristics of an image sensor integrated with Si-LED using a standard SiGe-BiCMOS process technology. The fabricated LEDs are classified into two types of avalanche and Zener in their breakdown mode. The avalanche type LED has found better emission efficiency. We have studied that the dependence of the distance between LED and APS on the discharge characteristics of the APS and found that over 500 μm is required to sunnress the effert from the LED.View full abstractDownload PDF (858K) -
Yoshinori MATSUI, Haruyoshi TOYODA, Naohisa MUKOSAKA, Munenori TAKUMI, ...Article type: Article
Session ID: IPU200266
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn this paper, we have developed a miniaturized image processing camera system with 1kHz frame rate, which includes image capture, processing and control output. This camera module is composed of 2D photo sensor (1kHz frame rate, 128×128 pixels, 256 analog levels) circuit. The camera has been minimized and integrated onto a 3cm × 4cm circuit board weighing 62.4grams. We have confirmed the miniaturized smart camera module is capable of image capture, feature extraction and real-time feedback control at 1000frame/sec. With it's advantage of compact size, light weight and high-speed processing capability, the camera can be applied to a wide range of applications such as three dimensional measurement, robot control, factory automation and vehicle vision system.View full abstractDownload PDF (862K) -
Shinya ITO, Shoji KAWAHITO, Hajime TAKASHIMA, Masaki SAKAKIBARAArticle type: Article
Session ID: IPU200267
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThe technology used is a 0.6/μm double-poly triple-metal CMOS process The sensitivity, dark current, fixed pattern noise, random noise, and image lag are compared in 4types of sensors ; 3-transistor, n+/p-sub photodiode (PD), 4-transistor n+/p-sub PD, 4-transistor n-well/p-sub PD, and 3-transistor (PMOS) P+/n-well PD.View full abstractDownload PDF (721K) -
Nobuhiro KAWAI, Shoji KAWAHITOArticle type: Article
Session ID: IPU200268
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn this paper, we describe the noise reduction effect of high-gain column amplifiers for CMOS image sensors. The noise at the back of the column amplifier can be reduced by amplifying the signal using the high-gain column amplifier when the signal is read out. A model of the noise calculation of the switched capacitor is established. The noise analysis shows that the high-gain column amplifier can reduce not only the noise at the back of it but also the noise of the amplifier itself.View full abstractDownload PDF (714K) -
Article type: Appendix
Pages App1-
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (74K) -
Article type: Appendix
Pages App2-
Published: September 26, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (74K)
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