This paper presents a calibration method for a high-frequency PLL synthesizer. As the frequency of the PLL synthesizer becomes high, a voltage-to-frequency conversion gain of a voltage-controlled oscillator (VCO) must be increased and PLL become sensitive to noise. The voltage-to-frequency conversion gain can be reduced by applying constant bias current to VCO and making the VCO minimum frequency offset from the zero frequency. In the conventional method, however, according to the large device variation of CMOS process, it is difficult to satisfy the desired frequency range and PLL might fail to lock. In our work, a self-calibration technique has been applied to adjust the tuning range automatically into the desired frequency band. Simulation result shows that the voltage-to-frequency conversion gain is reduced to 25% of the conventional VCO.