Abstract
As the technology scaling approaching nano-scale region, variability in device performance becomes a major issue in LSI design. In this report, measured variabilities from 0.35μm to 90nm processes are explained with a growing concern of within-die components. Variability impact on circuit performance is discussed. A possible approach for mitigating the variability is the introduction of layout regularity, and its effect is examined by test structures in a 90nm process and lithography simulation in a 45nm process. Our observation suggests that, from the standpoint of performance overhead incurred by the regularity enhancement, it is important to correctly enforce necessary and sufficient level of regularity for each technology node.
