A Dedicated Image Processing Engine Stacked with CMOS Image Array at 40nm CMOS Imager Technologies

Biay-Cheng Hseih; Khoi Le; Keith Honea; Sami Khawam; Hasib Siddiqui; Sergio Goma; RJ Lin; Chin-Hao Chang; Kuo-Yu Chou; Calvin Chao

doi:10.11485/itetr.40.40.0_5

40.40 Information Sensing Technologies(IST)

セッションID: IST2016-50

DOI https://doi.org/10.11485/itetr.40.40.0_5

会議情報

主催: Information Sensing Technologies(IST)

会議名: 情報センシング

開催日: 2016/11/17

A Dedicated Image Processing Engine Stacked with CMOS Image Array at 40nm CMOS Imager Technologies

*Biay-Cheng Hseih, Khoi Le, Keith Honea, Sami Khawam, Hasib Siddiqui, Sergio Goma, RJ Lin, Chin-Hao Chang, Kuo-Yu Chou, Calvin Chao

著者情報

キーワード: Re-Configurable Instruction Cell Array (RICA), Stacked BSI Image Sensor, Computational Photography

会議録・要旨集フリー

詳細

抄録

Current camera systems present a huge image signal processing (ISP) programmable limitation, since the ISP algorithm is mainly hard-coded via Application Processor. We'll present the prototype development result of a Re-Configurable Instruction Cell Array (RICA), a real time, low power reprogrammable ISP engine stacked with 8MP detector array fabricated in 40nm BSI CMOS imager technology. We believe this RICA stacked image sensor technology presents an efficient programmability solution to support adjacent IOT markets, and next generation computational camera technologies.

責任著者(Corresponding author)

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