Low phase noise of Fractional-N PLL utilizing GA

Abstract

This paper proposes an approach to reduce the phase noise of a fractional-N PLL synthesizer by using Generic Algorithm(GA). The fractional-N PLL synthesizers have been used especially in wireless communication devices recently because of its advantages but the synthesizers produce intrinsic phase noise due to the quantumizing error. In this work, the sequence of division for the counter in the synthesizer is calculated so that the phase noise may be minimized. This optimizing calculation needs a lot of computation but the use of GA enables us to obtain a solution.