ホモジニアスFPGAアーキテクチャ向けハードエラー復旧手法

抄録

FPGA fault detection consumes a great deal of test time compared to ASICs because FPGAs have complex structures. Moreover, re-placement and re-routing must be performed to avoid fault points. This operation causes the increase of recovery time and degrades performance. Therefore, we propose a fault detection method and develop placement and routing tools to avoid fault resources in tile and multiplexer level avoidance, respectively. In the evaluation, the detection method diagnosed a faulty multiplexer with six test configurations. The performance degradation of the fault FPGAs was slight.