2021 Volume 14 Pages E21-002-1-E21-002-9
We have developed a 5-in-1 fan-out wafer-level packaging (FOWLP) that integrates one fully operative artificial intelligence (AI) chip with approximately 2,500 pins and four memory chips for Internet of Things (IoT) modules. Three typical issues with FOWLP: (1) die shift, (2) wafer warpage and (3) fine redistribution layer (RDL) formation are solved by adopting a low elastic modulus mold resin and bonding a Si substrate on the backside of the reconfigured wafer. The developed package provides a die shift of less than ±5 µm, package warpage of 10.6 µm over 31 mm × 31 mm, and three-layer RDL formation with L/S = 10 µm/20 µm. Finally, function testing of the AI chip and memory chips using a computer circuit board are demonstrated. This study shows that FOWLP can be applied to future AI edge computing and large memory modules, and provides a direction for FOWLP process development for panel-level packaging, which may be able to ease module size restrictions.
