A Multilayer Process for 3D-Molded-Interconnect-Devices to Enable the Assembly of Area-Array Based Package Types

Abstract

Three-dimensional molded interconnected devices (3D-MID) extend the range of classical printed circuit boards (PCB) to the third dimension. Electrical circuits can be routed over any surface forms. This enables innovative applications and new design possibilities. The combination of circuit carrier, housing, and further functions results in an increased density of integration with decreased process effort. One limitation of recent 3D-MID technologies is their incompatibility with modern area-array based electronic packages. Usually the high I/O count of such package types makes routing in only one electrical layer impossible and necessitates multilayer structures. To meet the future requirements of 3D-MID, a compatible fine-pitch multilayer process is developed. In combination with an established 3D-MID metallization process, it allows the flip-chip mounting of area-array packages. A sample device with three metallization layers is fabricated. The mechanical and electrical multilayer properties are investigated.