Transactions of The Japan Institute of Electronics Packaging
Online ISSN : 1884-8028
Print ISSN : 1883-3365
Original Articles
Inter Chip Fill for 3D Chip Stack
A. HoribeF. YamadaC. FegerJ. U. Knickerbocker
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JOURNALS FREE ACCESS

2009 Volume 2 Issue 1 Pages 160-162

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Abstract

Three-dimensional (3D) integration is considered to be the most promising solution for the continuing improvement in device performance,[1] while the scaling of Si CMOS is approaching its economical and physical limits. Inter Chip Fill (ICF) resin, filled between the gaps of 3D stacked chips, is expected to improve the mechanical strength and corrosion resistance of such chips. Pre-applied resin, which is applied before the chip joining process, was evaluated for this application. The characteristics required for ICF materials are different from those for conventional flip chip underfills, because the ICF must fill much thinner, multiple gaps of the order of a few micrometers between the silicon dies for which there is no CTE mismatch.
In this paper, a new ICF resin was designed for the 3D chip stack. The polymerization and viscosity of the material at each joining process step were precisely optimized. As a result, we could confirm the applicability of pre-applied ICF materials to the 3D chip integration process joined by very low height solder bumps of an area array. We arrived at the idea of a novel Stack Joining process which could be effective to reduce chip stacking process costs and contribute significantly to higher reliability.

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© 2009 The Japan Institute of Electronics Packaging
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