Transactions of The Japan Institute of Electronics Packaging
Online ISSN : 1884-8028
Print ISSN : 1883-3365
ISSN-L : 1883-3365
Technical Papers
Development of High Productive Micro Solder Flip Chip Bonding Process
Daisuke SakuraiTakatoshi OsumiKazuya UshirokawaTakashi NakamuraTakatoshi Ishikawa
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ジャーナル フリー

2012 年 5 巻 1 号 p. 99-106

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To increase the productivity rate of the 3 dimensional system in package (SiP) used for electronics devices such as cloud computing and smart phones, the authors have developed a new micro solder flip chip bonding process. By this means, a higher-function and lower-cost SiP can be achieved. In the conventional process, more than 10 seconds of bonding time are needed to control metal oxide film of solder bump and the warpage of a thin chip. The paper suggest a flip chip process should be divided into the following processes; 1) the temporary bonding process i.e. the molten solder is rapidly diffused into an electrode under an inert gas atmosphere, and 2) the final joint process i.e. the solder bumps of multiple chips are all together bonded, while the warpage of chips are corrected under reductive gas atmosphere and pressure. The authors have verified that even when the fluxless process is used, such divided mechanism can shorten the time needed for bonding an IC chip with pitch and thickness of each 50μm to 0.25 seconds.

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© 2012 The Japan Institute of Electronics Packaging
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