2015 Volume 8 Issue 1 Pages 18-22
The increasing demand of advanced electronics devices with ever increasing of functionality and performance have driven semiconductor industry to scale down in feature size of the Integrated Circuits. The semiconductor industry still follows the Moore’s Law.
In order to package the increasing number of transistors per unit area, the packaging substrate also need to increase packaging density by going to fine line and fine vias. The organic dielectrics with E-less copper capability that are required in the laminated substrate industry. Copper cored laminates are also commonly used in the industry.
In this paper we present factors that affect the formation of fine line on organic dielectrics. The compatibility of fine line process to the substrate process has been evaluated in this study. Test vehicles for evaluation of 2 μm fine line are designed and built. In addition, it is desirable to process fine line on large panel greater than 12" format for cost down reason. Fine line that is as small as 2 μm has been evaluated on panels with the size as large as 508 × 508 mm in this study.
