抄録
The residual stress and warpage of a device embedded substrate (DES) is evaluated using a Si chip including a piezo-resistive sensor. Two types of DESs are fabricated to investigate the effect of substrate structure on residual stress: a device mounted on the surface of a core substrate (core surface mounted type DES) and a device placed inside a through cavity of a core substrate (core cavity type DES). Both DESs have four conductor layers with two build-up ABF (Ajinomoto Build-up Film) layers. For the core cavity type DES, the effect of cavity clearance from 0.15 mm to 1 mm between the core wall and embedded chip is also investigated. The embedded devices are 9 × 9 mm2 piezo-resistive sensor chips of 200 μm in thickness, and the core is adjusted to the Si chip thickness. The residual stress induced from the fabrication process is obtained from measuring the resistance value of the piezo-resistive sensor before and after chip embedding. After measuring the residual stress, the warpage for each type of DES is observed using the shadow moiré interferometry method with the temperature changing from 25°C to 260°C. The relationship between the residual stress and warpage is discussed with respect to the substrate structure symmetry and balance.
