出力リプル打ち消し回路によるDCPTの入力電力低減と周波数特性改善の検討

抄録

A novel circuit technology for input power reduction and frequency response improvement of DCPT was studied. First. proportionality between output ripple and output winding voltage ripple of DCPT was proved by circuit analysis. Secondly, a circuit aiming to cancel the output ripple by the winding voltage ripple was designed and its basic fuction was confirmed by experiments using a 60 Hz-driven DCPT (rated input power=80 W; natural frequency of reactor=12 kHz). As a residual pulsive voltage due to the natural oscillation of the reactor was observed in every half-cycle of 60 Hz, a time delay of about 60 microseconds was added to the cancellation circuit to reduce the pulse amplitude. Finally, the input power was reduced to 1/5 of that of the conventional DCPT and the frequency response nearly equal to that of ACPT (i.e., the reactor itself) was attained.