抄録
The purpose of this paper is to propose the circuit for autonomous determination of optimal NN (neural network) structure for the applied problems and to implement the circuit on an FPGA (field programmable gate array) to test its basic functions. Many research activities to determine optimal structure of the NN have been done so far, however, no NN LSI (neuro-chip), which can execute NN functions quickly, can determine appropriate network structure autonomously, i.e. its network structure is determined by using software running on a PC (personal computer) or a WS (work station). In this paper, to determine the optimal network structure for the neuro-chip autonomously (i.e. without a PC or a WS), we propose hardware implementation of GA (genetic algorithm) operations, which can be embedded on the neuro-chip.
