IMPLEMENTATION OF A MONO INSTRUCTION SET COMPUTER ON A RADIATION-HARDENED OPTICALLY RECONFIGURABLE GATE ARRAY

抄録

Radiation tolerant optically reconfigurable gate arrays (ORGAs) have been developed [1]-[5]. These radiation-tolerant optically reconfigurable gate arrays have two characteristics: high total ionizing dose and soft error tolerance and fast reconfiguration. To improve the performance of radiation-tolerant optically reconfigurable gate arrays, we proposed the Mono Instruction Set Computer (MISC). MISC is a processor architecture that reduces the number of instructions to one by relying on reconfiguration of the circuit with programmable devices to change functions. As a result, MISC can be implemented in a small gate array area and can provide a higher clock frequency than RISC (Reduced Instruction Set Computer), which is currently widely used as a processor architecture. In addition, since the implementation area is small, performance can be improved by implementing multiple MISC processors in parallel in the same area as a RISC processor. In this study, we implemented the arithmetic part (ALU) of a 4-bit MISC processor with six functions (logical AND, logical OR, addition, subtraction, multiplication, and division), and compared and evaluated it with an implemented RISC processor. The results confirm that MISC processors have higher performance than RISC processors. In addition, a 32-bit MISCALU was implemented and its performance was verified with maximum operating frequency and footprint