半導体埋め込み型配線応力評価用センサの開発

抄録

A 3-D stacking structure of silicon chips has been introduced to satisfy the needs of higher performance and multi functionality of electronic devices. The miniaturization and high densification of interconnections and semiconductor devices, however, would cause a fluctuation of the residual stress during the fabrication process and under operation. Since high residual stress degrades the performance of electronic devices and also long term reliability, it is important to monitor and control the local residual stress. In this study, a strain sensor that is embedded in a silicon chip and can measure the residual stress nondestructively was developed by applying piezoresistance effect of single crystal silicon. The stress sensitivity at room temperature was 1.3 MPa/Ω, which can measure the change of the residual stress sufficiently. Then, this sensor was applied to the measurement of the local residual stress between Cu interconnections and the high residual stress around the interconnections was verified.