最適化シンポジウム講演論文集
Online ISSN : 2424-3019
会議情報
106 チップマウンタシステムの実装時間最適化問題への遺伝的アルゴリズムの適用
宮嶋 隆司中村 正行小林 光征小杉 俊
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会議録・要旨集 フリー

p. 31-36

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抄録
This paper presents an optimization method of production efficiency on the placement time in the chip mounter system. We have approached this production efficiency by control software. Placement time changes greatly by the performance of the chip mounter and the configuration of the system. The problem is how to distribute parts and parts feeders to each chip mounter. We have proposed a distributing method by GA. We describe three items. The first is suggestion of a design index value. The second is correspondence to multi-purpose optimization. And the third is handling of a constrain. Several numerical experiments about some systems composed of plural chip mounter with different performance were done. It was confirmed that our proposed method had effectiveness more than conventional method through the results of numerical experiments. Furthermore, practical examples to the produced utility system are shown.
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© 2002 一般社団法人 日本機械学会
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