Abstract
Tins paper describes a new recon.flgurabie processor architecture for high frame rate visual processing. This architecture employs a 2-D mesh processing element (PE) array in which the PEs can he configured to operate as SIMD arrays or operation-pipeline trees depending on image processing algorithms so that maximum on-chip memory consumption is reduced, To achieve high on-chip memory utilization, the architecture features that. the instruction register in each PE is mapped in its local memory space and that tire ALU network and the local memory network can be configured independently. Experimental results show that the proposed architecture effectively utilizes both of the SIMD and operation pipeline modes.
