The Proceedings of International Symposium on Seed-up and Service Technology for Railway and Maglev Systems : STECH
Online ISSN : 2424-3167
2003
会議情報
B303 DEVELOPMENT OF THE FAIL-SAFE SINGLE CHIP RISC-CPU BOARD
Toshihiko KajiwaraSei TakahashiMunehisa TairaHidetaka SaegusaHideo Nakamura
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会議録・要旨集 フリー

p. 271-275

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抄録
One configuration of FS-Computer is composed of dual-CPU, dual-peripheral circuits and checking-circuits which supervise dual-CPU and peripheral circuits always running synchronously each other. We introduced the new idea of safety to implement such FS-CPU within a single chip LSI fail-safely, namely using PN-code to detect the failure of intemal circuits and so on. In this article, we address the concept of the safety of dual-CPU in a single chip and its verification.
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© 2003 The Japan Society of Mechanical Engineers
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