抄録
A numerical technique for optimizing the thermal design of power semiconductor modules for mobile communication systems is described. It uses a finite element program for parallel-processing computers to analyze the thermal resistances between the heat-generating layer and the bottom surface of a semiconductor wafer. Since there is a total of more than ten million nodes in the program, it can calculate the temperature distribution inside each heat-generating cell in the semiconductor substrate. The technique was applied to a steady-state analysis to estimate the thermal resistances of collector-up GaAs heterojunction bipolar transistors (HBTs) for small high-power amplifiers used in cellular phones. The results show that the thermal resistances of collector-up HBTs is reduced by 64% of that of normal emitter-up HBTs. They also show that the thermal interface between each collector-up HBT is not negligible even if they are located on a novel thermal via.
