抄録
We have been studying the via-programmable structured ASIC architecture "VPEX3 (Via-Programmable logic using EXclusive-or array 3)", which can realize arbitrary logic by customizing only via layers. Our previous research found that VPEX3 cannot achieve the same maximum operation speed as ASIC and other mask-programmable devices. In this paper, we propose and evaluate a new architecture "VPEX3S". In this architecture, the output drivability of LEs is strengthened, and the via resistance between LEs is reduced in order to decrease the critical path delay. From an evaluation using logic synthesis, maximum operating speed of VPEX3S was found to be improved by about 34% compared to VPEX3. On the other hand, the circuit area was estimated to be 50%-60% larger than that of VPEX3 from the logic synthesis result. This is because the LE size increased by a factor of 1.85 because of the increase in transistor gate width and the number of vias. However, after placing and routing, the implementation area was estimated to be comparable or smaller. This is because the number of routing resources determines the area. As a result, the proposed architecture VPEX3S can realize the same speed performance as ASICs, with 3.3-4 times larger implementation area.
