Abstract
For many mathematical applications, the conventional coordinate rotation digital computer (CORDIC) algorithm can achieve high efficiency. However, the iterative procedure of the conventional CORDIC algorithm is inefficient owing to its rotation strategy. Chen et al. proposed a CORDIC algorithm with an improved rotation strategy to reduce the number of unnecessary iterations of the CORDIC algorithm. As a result, the calculation speed can be improved to four times than that of the conventional CORDIC hardware when the improved rotation strategy can finish its own functions within one clock cycle. However, the complexity of the improved rotation strategy is greatly increased, making it difficult to finish each rotation within one clock cycle. To overcome this difficulty, a hardware architecture for CORDIC with an improved rotation strategy is proposed to ensure that the improved rotation strategy can be finished within one clock cycle.
