Reduction of SiC-MOS Interface Traps and Improved MOSFET Performance by Phosphorus Incorporation into Gate Oxides

Abstract

We have developed a new technique, POCl₃ annealing, to improve 4H-SiC MOS interface properties. In this paper effects of phosphorus incorporation into the gate oxide by POCl₃ annealing on electrical properties of 4H-SiC MOS devices are introduced. POCl₃ annealing is more effective to reduce interface state density (D_it) and near-interface traps (NITs), and to improve channel mobility compared with the conventional NO annealing. High-low C-V characteristics at room temperature, cyclic C-V characteristics at 80 K, and thermal stimulated current measurements for MOS capacitors revealed that most of D_its near the conduction band edge and NITs are greatly reduced to the detection limit level. I-V characteristics of MOSFETs showed that the channel mobility was improved to be 89 cm²/Vs, which is 3 times higher than that of the NO annealed MOSFETs. Chemical bond structures at the interface for NO and POCl₃ annealed samples are also investigated by X-ray photoelectron spectroscopy.