Cyclic reservoir neural network circuit for 3D IC implementation

抄録

Reservoir computing is a computational model inspired by the information processing of the brain. In particular, it shows high performance in time-series processing using recurrent neural network dynamics despite its simple structure. Furthermore, a simple learning algorithm only in the output layer is sufficient for training the entire network. Therefore, its efficient hardware implementation is highly expected. However, it is important for a reservoir network to have a rich variety of dynamics to deal with complex time-series information. To introduce rich dynamics in the reservoir network without degrading the network stability, a chaotic neural network reservoir was proposed. In this paper, we propose a cyclic reservoir neural network circuit suitable for a stacked three-dimensional (3D) integrated circuit (IC). Through 3D IC fabrication technology, in which several semiconductor substrates are vertically stacked and connected by through-silicon vias (TSVs), we can efficiently integrate the chaotic neural network reservoir circuit. We designed and fabricated a prototype IC chip of the proposed circuit with a TSMC 180 nm CMOS semiconductor process. We verified its operation through SPICE and MATLAB simulations and preliminary experiments with the fabricated prototype chip.