Structure-aware tile-level scheduling for irregular CNNS on PE-array accelerators

抄録

Lightweight CNNs such as MobileNetV2, ShuffleNetV2, and ResNet18 exhibit irregular computation patterns—including depthwise separable chains, residual shortcuts, and branch-merge structures that form complex dependency graphs. On PE-array accelerators with limited on-chip buffers, conventional layer-wise and heuristic pipelined scheduling fails to exploit these dependencies, resulting in synchronization stalls, weight-bank contention, and redundant computation from spatial tile overlap. We proposed a structure-aware tile-level scheduling framework that explicitly models fine-grained dependencies under fixed hardware resources. The framework constructs an operator dependency graph into a tile-level DAG, and enables cross-layer tile pipelining through dependency-preserving scheduling. A PPO-based scheduler is trained to minimize makespan while penalizing weight conflicts and spatial overlap redundancy. Experimental results show that the proposed method consistently outperforms layer-sequential and layer-pipelined baselines, achieving up to 83% latency reduction over layer-wise execution and up to 10% improvement over pipelined scheduling. Average PE utilization is improved by 6–10% without increasing hardware parallelism, indicating that performance gains arise from dependency-aware tile ordering and reuse-aware PE allocation rather than architectural scaling.